1. Yuri Velikzhanin (yuri@hep1.phys.ntu.edu.tw) NuTel TV meeting, June 13 (Friday), 2003 Status of electronics for NuTel prototype

2. PMT Preamp. UV filter Hamamatsu 8x8 PMT 16-channels preamplifier Trigger FADC DAQ RAM PMT Preamp. UV filter FADCTriggerRAM Detector pair Stop 32 – channels DCM (Data Collection Module) in cPCI 10 bit x 40 MHz 2 RAM x 256 x 16 per channel Mirror FPGA Schematics of new electronics

3. Main modifications during last month 1.Change design from VME onto Compact PCI (cPCI) due we need fast readout speed for making a second-level software trigger. 2.Delete all interconnections for trigger signals due we don’t need statistics (uniformity, isotropy…) – there will be around one event per year. Loosing less 1% only! 3.Use two triggers: first-level hardware trigger like logical OR of triggers inside all DCM, and second-level software trigger. One Data collection module processes signals from 4x8 pixels (half of MPMT) from one detector. 4.Use 25nS (one clock) gate for trigger logic due most of signal are inside one clock (from our simulations).

4. RAM buffer stop readout Old version: two cycle buffers per channel with depth 256. 1 2 Marked memory cells for readout 256 x8 256 FIFO 1Kx16 FIFO 1Kx16 PCIPCI

5. Expected layout of DCM Trigger FPGA J1 J2 P1 trigger clock main FPGA main FPGA ADC PLX PCI9054 x2 sides P2 P3 ? Config. CPLD Flash memory LVDS J3 ? LOCALBUSLOCALBUS cPCI bus connectors

6. Clocking Clocking/timing Trigger FPGA FIFO FPGA FIFO FPGA 40 MHz oscillator to ADC terminators 80 MHz, 40 MHz divider regreg regreg 80 MHz comparator external 40 MHz MUX regreg 40 MHz with good 0-1 time ratio DCM x 32 (200) Clock distributor module 32x2 outputs Global Clocking module 80 MHz, 40 MHz 80 MHz oscillator 80 MHz oscillator ? ~2 km. away Global Clocking module 80 MHz oscillator ?

7. How to calculate N p.e./1 clock ANAN A N+1 15/16A N Change in amplitude due new photoelectrons: Δ A = A N+1 – 15/16A N N = Δ A / gain ADCReg. >>4 – ANAN A N-1 1/16A N 1/16A N-1 15/16A N-1 Reg. – 15/16A N-2 Δ A N-1 = A N-1 – 15/16A N-2 Schematics of firmware (inside FPGA) ΔAΔATrigger

8. Time interval for trigger From simulation > 90% of signal comes during one ADC clock, so time interval will be one clock – 25 nS. There will be used two thresholds logic: Reg. ΔANΔAN comparator Programmable High-level threshold (individual for every channel) To trigger logic Schematics of firmware (inside main FPGA)Trigger comparator Programmable Low-level threshold (individual for every channel) Reg. HLT LLT

9. Trigger Trigger array of one DCM

10. DAQ configuration TRIGGERTRIGGER BRIDGEBRIDGE DCMDCM CPUCPU DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM BRIDGEBRIDGE DCMDCM DCMDCM DCMDCM DCMDCM TRIGGERTRIGGER BRIDGEBRIDGE DCMDCM CPUCPU DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM DCMDCM BRIDGEBRIDGE DCMDCM DCMDCM DCMDCM DCMDCM Ethernet Not fixed (discussable) !!!

11. PXI chassis GX7000

12. Data flux inside main FPGA FIFO 1Kx16 1 2 256 1 2 1 2 1 2 1 2 1 2 1 2 1 2 datafromADCdatafromADC to local bus x16 FIFO size: if 4 time slots: 1024/8/4 = 32 events! But we need to add event number: 1024/8/5 = 25 events! event number

13. Data flux inside one DCM Trigger FPGA J1 J2 P1 main FPGA main FPGA PLX PCI9054 P2 P3 ? Config. CPLD Flash memory LVDS J3 ? LOCALBUSLOCALBUS cPCI bus connectors main FPGA main FPGA D15-D00 D31-D16 Ch.1-8 Ch.9-16 Ch.17-24 Ch.25-32 D31-D00

14. Possible data flux inside one chassis CPU RAM Bank#1 RAM Bank#2 RAM Bank#3 RAM Bank#4 from cPCI DMA Second-level trigger DMA to Ethernet

15. Schedule for electronics 1.Before August 1: have 2 DCM and 4 new preamplifiers 2.August-September: debugging first iteration, hope a final 3.October-December: making a final firmware, two Trigger modules (simple), software… 4.January: Mass production 5.February – March: Mass debugging + start integration test 6.End of March - beginning of April: end of the first period of NuTel project (moved ~one month later due cPCI design instead VME) Problems 1.Optics – main problem now 2.MPMT – we have only 11 pieces, need 16, could Palermo people give as some pieces? When? If not – we need to bye. We’ll need its before February. 3.HV power supply is in VME. Already have one (for 8 MPMT), need another one.