1. AGATA Pre-processing team report AGATA Week, July 2008

2. Overview of talk The team Progress on carrier Progress on mezzanines Some problems fixed since AGATA week Readiness for triple cluster tests (October) Finances Timescales Conclusion

3. Reminder of team and responsibilities IPN Orsay –Carrier VHDL design (FPGA2- trigger distribution) –Carrier VHDL production code –Carrier commissioning (production run of 34 cards) –Original carrier design INFN Padua –Carrier rework (prototype and pre-production) –Carrier VHDL (release 0 for initial tests) –Carrier VHDL (FPGA 0- data readout) –Delivery of 6 tested carriers for October tests –GTS Mezzanine CSNSM Orsay –Segment mezzanine (hardware and VHDL) –Core mezzanine (hardware and VHDL) –Production run of core and segment mezzanines IPHC Strasbourg –Supply of MWD code for use in core and segment mezzanines in “black box” format STFC RAL and LPC CAEN –VHDL code for carrier readout (PCIe and proprietry “FASTER” protocols) Team size –On average between 10 and 15 people are working on this project at the moment.

4. Progress since last AGATA week- Carrier Carrier rework –commissioning of prototype finished November 2007 –small revisions made to PCB layout Dec07/Jan08 –pre-production version manufactured. Delivered early April 2008 –pre-production version commissioned April; ready to use May 2008 Photo- INFN Padova

5. Progress since last AGATA week- Carrier –JTAG test code written (R.Matson, RAL) –VHDL code development (Orsay and Padua) –Test system set-up (Orsay) –Carrier production run. 5 cards from Padua- PCB received, assembly started (due end July) Remaining cards (Orsay)- purchasing started. Problems with location of funding being resolved Photo- INFN Padova

6. Progress since last AGATA week- Mezzanines Segment and Core Mezzanine rework –Commissioning of prototype v2.0 finished December 2007. –small revisions made to PCB layout Dec07/Jan08 (v2.0 to v2.1) –Final v2.0 prototype tests on carrier using BERT to validate high speed links Feb 2008 Padua. –Pre-production version (v2.1) manufacturing started Feb 2008, Delivered April 2008 (3x core), May 2008 (10x segment) –Commissioning for 1 st pre-production version (v2.1) segment cards completed mid-May 2008 –pre-production version (v2.1) commissioning for core and 4 more segment cards due for completion end July 2008. Photos- CSNSM Orsay

7. Progress since last AGATA week- Mezzanines Core and segment mezzanine production run. –Despite successful February BERT tests, some improvements to MGT clock jitter have been found. –Power supplies and clock routing are being modified before the full production run. –Modifications tested on pre- production cards 10 more of the existing segment card design are being made now for October tests (€16k) They will be modified to include the same changes as will be made to the other cards Photos- CSNSM Orsay

8. Testing pre- production cards May –Carrier and 2 segment mezzanines available for test. –Digitiser set up in Padova Last week of May –first traces with pulser through digitiser and pre-processing

9. Carefully attended by the LLP team, on May 22, 2008, THE FIRST AGATA TRACE made its way from the digitiser to the ATCA-carrier, via segment mezzanine.

10. Digitized, optically-transmitted and pre-processed AGATA traces May 28, 2008

11. Testing pre- production cards May –Carrier and 2 segment mezzanines available for test. –Digitiser set up in Padova Last week of May –first traces with pulser through digitiser and pre-processing June –Investigate the 2 “unusual” traces End June- –Taking spectra with 1 segment card (6 ch) on 1 carrier using AGATA detector and digitiser Early July (now)- –Connect 2 carrier cards and exchange trigger data End July –build up to full configuration (2 carrier cards, 6 segment cards, 1 core card, 1 GTS) for tests with 1 crystal and full digitiser.

12. Progress since last AGATA week- fixing problems Fast serial- parallel readout mezzanine to carrier –Synchronisation problems fixed- now working at full speed. Intermittent connection to carrier DPRAM –Used to test JTAG (blind test- found faulty pin) –Discussions held with assembly company to prevent recurrence Trace corruption seen in first results –Tracked down to a VHDL error- now fixed –Resulted in stringent jitter testing and improvements to mezzanines Plot from INFN Padova and CSNSM Orsay

13. Readiness for Tests with Triple cluster in October.

14. Cost Savings Investigated using slower (cheaper) FPGAs on the mezzanines. Decided against this due to risk and also revised FPGA pricing. FPGA- Xilinx assisted pricing obtained. About 30% savings. Cut out segment offset fibres for LNL phase (€10k saving)

15. Funding for production run Carrier –2 pre-production + 5 cards funded from Italy, built in Italy –Remaining 34 cards (including 3 spares) will be built in France –Cost €178k –Some funds available in France –Missing funds coming from Germany (FPGA order) (complete) Sweden funds transfer plus orders for PCBs and other FPGAs (not complete) Core and segment mezzanines –All 140 (108 segment + 18 core + spares) will be built in France –Cost €310k –Some funds available in France –Missing funds coming from Germany (FPGA Order) (complete) Loan from GANIL (EXOGAM) against future funds transfer, (loan complete)

16. Compare to planned timescales Jan 2007 ReportNov 2007 ReportJuly 2008 Report Carrier update Layout PhaseDone Q1 2007 Segment & core mezzanine update Start of layout phase Done Q1 2007 Expect to get prototypes of both by July 2007 Deliver prototypes July 2007 Delivered July 2007 (Carrier and segment mezzanine*) Test prototypes Autumn 2007Expected to complete Nov. 2007 Completed Nov- Dec 2007 Designs finalised Dec 2007Expected to complete Nov - Dec. 2007 Dec 2007-Jan 2008 Production beginning 2008 (phased delivery) Phased, starting beginning of 2008 Pre-production cards early 2008 Pre-production cards delivered April/May 2008 Pre-production tests complete March 2008May 2008 Build up system- test 1 cluster July 2008 1 st Phase production (triple cluster) Commissioning Apr 2008 onwards Manufacture now. Commissioning July- Sept 2008 2 nd Phase production (5 triple clusters) Ready now- depends on funds. End 2008? VHDL and software 1 st Release Autumn 08 * Core mezzanine prototype assembly was delayed until tests were complete on segment mezzanine. Designs were ready for delivery in July 2007 if required.

17. Conclusions Timescales are tight but with continued hard work the triple cluster test date Oct 2008 is achievable (but there is no schedule contingency) Funding has been a big problem- its in the wrong place and significant effort has been diverted into moving it to where it can be used. Bigger spend on travel than expected. Huge amount of work by the whole pre-processing team: –Long periods spent away from home by some people working in Padua. –Long hours were worked over the last 18 months by some members of the pre-processing team. Significant progress has been made with end to end tests, but we’ve still got more to do so we need to keep up or even increase the effort.

18. Thanks Thank you to the pre-processing team for their very hard work!