1. AIDA FEE64 production report January 2011 Manufacturing Power Supply FEE64 revision A “3 hour test” 19th January 20111

2. Manufacturing FEE64: All components purchased and with Jaltek PCB: ExceptionPCB have failed to make the board at the final stage. They put too much copper on the outer layers. The final etch then needs to be longer and this compromises track width of the finer tracks. The board will now be delivered to Jaltek on 24 th January for 10 working day assembly. Mezzanine: Pcbs were delayed from ExceptionPCB due to snow! Assembled boards have questions about the quality of the solder joints. Currently in discussion with Jaltek. Boards returned to Jaltek today for joint x-ray and re-work 19th January 20112

3. Power Supply One PowerStax system has been purchased by Liverpool. This is being assembled, tested and then used at Daresbury for evaluation and testing the first FEE64 from Jaltek. Liverpool are making a cable using the FEE64 connectors and low loss wire. 8 FEE64 board power system and two cables delivered to Daresbury today. It will be connected to the mezzanine power supply of an existing board to test for any problems in changing resolution. 19th January 20113

4. FEE64 revision A “3 hour test” Purpose Validate the revision A design prior to full manufacture. The production line will be held for one day and approval must be given by midday. Scope 1.Test the power supplies for correct function and noise. 2.Test the SDRAM, Gbit, PowerPC and Flash memory. 3.If time allows the data links with the FADC devices and the clock distribution will be tested. 4.A Mezzanine, with known performance, will be used to test the new buffer and slow ADCs. Whatif Failure to approve will require a £2000 set-up fee to re-start production. The majority of the components will be saved for a potential new pcb (£14,500). 19th January 20114

5. FEE64 revision A “3 hour test” Preparation Validating the test firmware using a prototype board and causing faults to check the error reporting. Testing a power system using a blank pcb prior to test with the first boards. Creating the firmware to work with the new ADCs for the ASIC readout. 19th January 20115