1. FEE Electronics progress
PCB layout
30th April 2009

2. Layout progress All data paths routed to +/- 2pS
Control paths routed from FPGA
30th April 2009

3. Layout to do Complete memory Gbit Ethernet.
ADC output signals to the FPGA.
Discriminator signal connections to the FPGA
Mezzanine connector signal definition
Clock distribution to the ADCs
Power supply blocks and delivery planes.
FPGA configuration memory.
Temperature sensors, RS232, LEDs etc.
30th April 2009

4. Collaboration with Detector Systems Development Group of TBU
Collaboration with Detector Systems Development Group of TBU. (Technology Business Unit )
Currently :
Bit stream successfully generated and working with LINUX.
Next steps :
Tuning the Ethernet firmware for maximum performance.
Create a DMA peripheral and check performance.
Create a memory test and configuration system.
30th April 2009