1. AIDA ASIC review Davide Braga Steve Thomas ASIC Design Group
14 January 2009

2. Top level

3. Analogue input and bias reference

4. Digital block and control register

5. Analogue outputs

6. Remaining work: Time-scale: Layout of bias pads
Wiring between control register and DACs
Connection of mux output amplifier
Power supply distribution, to minimise resistance
Top level checks, including metal coverage and antenna rules
Top level simulation, with final schematic (compatible with layout)
Update of documentation (project spec, pad definitions, waveforms)
Time-scale:
Design submission on 26 January
Request for quotation 15 January? [need to specify exact die size and chip numbers]