1. PLDS Mohammed Anvar P.K AP/ECE Al-Ameen Engineering College

2. PLDs – Programmable Logic Devices (PLD) General purpose chip for implementing circuits Can be customized using programmable switches – Main types of PLDs PLA PAL ROM CPLD FPGA – Custom chips: standard cells, sea of gates

3. Chapter 3 - Part 2 3 ROM, PAL and PLA Configurations (a) Programmable read-only memory (PROM) Inputs Fixed AND array (decoder) Programmable OR array Outputs Programmable Connections (b) Programmable array logic (PAL) device Inputs Programmable AND array Fixed OR array Outputs Programmable Connections (c) Programmable logic array (PLA) device Inputs Programmable OR array Outputs Programmable Connections Programmable Connections Programmable AND array

4. Programmable Logic Array (PLA) – Use to implement circuits in SOP form – The connections in the AND plane are programmable – The connections in the OR plane are programmable f 1 AND plane OR plane Input buffers inverters and P 1 P k f m x 1 x 2 x n x 1 x 1 x n x n

5. Gate Level Version of PLA f 1 = x 1 x 2 +x 1 x 3 '+x 1 'x 2 'x 3 f 2 = x 1 x 2 +x 1 'x 2 'x 3 +x 1 x 3

6. Customary Schematic of a PLA f 1 = x 1 x 2 +x 1 x 3 '+x 1 'x 2 'x 3 f 2 = x 1 x 2 +x 1 'x 2 'x 3 +x 1 x 3 f 1 P 1 P 2 f 2 x 1 x 2 x 3 OR plane AND plane P 3 P 4 x marks the connections left in place after programming

7. Page 7 PLA Logic Implementation Example: Equations Personality Matrix Key to Success: Shared Product Terms 1 = asserted in term 0 = negated in term - = does not participate 1 = term connected to output 0 = no connection to output Input Side: Output Side: Reuse of terms F 1 1 0 1 0 0 OutputsInputsProduct term A 1 - 1 - 1 B 1 0 - 0 - C - 1 0 0 - F 0 0 0 0 1 1 F 2 1 0 0 1 0 F 3 0 1 0 0 1 A B B C A C B C A F0 = A + B C F1 = A C + A B F2 = B C + A B F3 = B C + A

8. Page 8 PLA Logic Implementation Example Continued - Unprogrammed device All possible connections are available before programming A B C F0 F1 F2 F3

9. Page 9 PLA Logic Implementation Example Continued - Programmed part Unwanted connections are "blown" Note: some array structures work by making connections rather than breaking them A B C F0 F1 F2 F3 AB BC AC BC A

10. Page 10 PLA Logic Implementation Alternative representation for high fan-in structures Short-hand notation so we don't have to draw all the wires! X at junction indicates a connection Notation for implementing F0 = A B + A B F1 = C D + C D A B C D AB+AB CD+CD AB CD AB Unprogrammed device Programmed device

11. Page 11 PLA Logic Implementation Design Example F1 = A B C F2 = A + B + C F3 = A B C F4 = A + B + C F5 = A  B  C F6 = A  B  C Multiple functions of A, B, C

12. Programmable Array Logic (PAL) – Also used to implement circuits in SOP form – The connections in the AND plane are programmable – The connections in the OR plane are NOT programmable f 1 AND plane OR plane Input buffers inverters and P 1 P k f m x 1 x 2 x n x 1 x 1 x n x n fixed connections

13. Example Schematic of a PAL f 1 P 1 P 2 f 2 x 1 x 2 x 3 AND plane P 3 P 4 f 1 = x 1 x 2 x 3 '+x 1 'x 2 x 3 f 2 = x 1 'x 2 '+x 1 x 2 x 3

14. 55:032 - Introduction to Digital DesignPage 14 PAL Logic Implementation Design Example: BCD to Gray Code Converter Truth Table K-maps Minimized Functions: A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X X X X X X X 0 0 0 0 1 1 0 0 0 0 X X X X X X Y 0 0 1 1 1 1 1 1 0 0 X X X X X X Z 0 1 1 0 0 0 0 1 1 0 X X X X X X AB CD 00011110 00 01 11 10 D B C A 00X1 01X1 01XX 0 1 XX K-map forW AB CD 00011110 00 01 11 10 D B C A 01X0 01X0 00XX 00XX K-map forX AB CD 00011110 00 01 11 10 D B C A 01X0 01 X 0 11XX 11XX K-map forY AB CD 00011110 00 01 11 10 D B C A 00X1 1 0X0 01XX 10XX K-map for Z W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D

15. 55:032 - Introduction to Digital DesignPage 15 PAL Logic Implementation Programmed PAL: 4 product terms per each OR gate Minimized Functions: W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D

16. 55:032 - Introduction to Digital DesignPage 16 PAL Logic Implementation Code Converter Discrete Gate Implementation 4 SSI Packages vs. 1 PLA/PAL Package! 1: 7404 hex inverters 2,5: 7400 quad 2-input NAND 3: 7410tri 3-input NAND 4: 7420 dual 4-input NAND

17. 55:032 - Introduction to Digital DesignPage 17 Another Example: Magnitude Comparator A K-map forEQ 1000 0100 0010 0001 AB CD 00011110 00 01 11 10 D B C AB CD 00011110 00 01 11 10 D B C A 0111 0011 0000 0010 K-map forGT AB CD 00011110 00 01 11 10 D B C A 0000 1000 1101 1100 K-map forLT 0111 1011 1101 1110 AB CD 00011110 00 01 11 10 D B C K-map forNE A PLA Logic Implementation

18. Comparing PALs and PLAs – PALs have the same limitations as PLAs (small number of allowed AND terms) plus they have a fixed OR plane  less flexibility than PLAs – PALs are simpler to manufacture, cheaper, and faster (better performance) – PALs also often have extra circuitry connected to the output of each OR gate The OR gate plus this circuitry is called a macrocell

19. Macrocell f 1 back to AND plane DQ Clock Select Enable Flip-flop OR gate from PAL 0101

20. Combinational and Sequential PLDS 16L4 PAL – Combinational Logic – Up to 16 inputs – 32 bit & bit-bar lines – Up to 4 outputs – Up to 7 product terms per output – 1 product term/output for tri-state control – Input, Output, Bi-driectional bus (on per output basis) – Note fuse numbers (early technology)

23. 16R4 PAL – Sequential Logic – 16 inputs (counting feedback into array from DFFs) – Again 32 bit & bit-bar lines – 4 outputs (Q outputs from 8 DFFs) – Up to 64 product terms – The flip-flops are all controlled by a common clock which is tied directly to pin 1 on the device. – pin 11, which is used as a dedicated input for the output enable of the flip-flops.

25. Simple PLDS PLD 22V10 – Combinational/Sequential Logic – PAL devices are most commonly used SPLD – Eg: PAL 22v10 – II input pins that feed the AND plane and an additional input that can serve as Clock input – The OR gates are of variable size, ranges from 8 to 16 inputs – From 8 to 16 product terms per output – Each out put pin has tristate buffer,which allows the pin to optionally be used as input pin – Introduction of Macro cell-the circuitry between OR gate and an out put in PAL – Combinational and/or sequential logic in 1 PLD

27. 22V10 macrocell

28. Complex Programmable Logic Devices (CPLD) – SPLDs (PLA, PAL) are limited in size due to the small number of input and output pins and the limited number of product terms Combined number of inputs + outputs < 32 or so – CPLDs contain multiple circuit blocks on a single chip Each block is like a PAL: PAL-like block Connections are provided between PAL-like blocks via an interconnection network that is programmable Each block is connected to an I/O block as well

29. Structure of a CPLD

30. Internal Structure of a PAL-like Block – Includes macrocells Usually about 16 each – Fixed OR planes OR gates have fan-in between 5-20 – XOR gates provide negation ability XOR has a control input

31. More on PAL-like Blocks – CPLD pins are provided to control XOR, MUX, and tri-state gates – When tri-state gate is disabled, the corresponding output pin can be used as an input pin The associated PAL-like block is then useless – The AND plane and interconnection network are programmable – Commercial CPLDs have between 2-100 PAL-like blocks

32. Example CPLD – Use a CPLD to implement the function f = x 1 x 3 x 6 ' + x 1 x 4 x 5 x 6 ' + x 2 x 3 x 7 + x 2 x 4 x 5 x 7

33. The Xilinx 9500-series CPLD The internal PLDs are called Configurable Functional Blocks (FBs or CFBs) Each FB has 36 inputs and 18 Macrocells (effectively a “36V18”) Each CLPD is packaged in a plastic-leaded chip carrier (PLCC) The number of I/O pins are much less than the total number of Macrocells in family of devices

34. Xinlinx CPLDs

35. Architecture of Xilinx 9500-family CPLD Global set/reset Global 3 state control Global Clock 36 Signal pins 18 outputs 18 Output enable signals 18 Output enable signals

36. XC9500 I/O Block

39. FPGA – SPLDs and CPLDs are relatively small and useful for simple logic devices Up to about 20000 gates – Field Programmable Gate Arrays (FPGA) can handle larger circuits No AND/OR planes Provide logic blocks, I/O blocks, and interconnection wires and switches Logic blocks provide functionality Interconnection switches allow logic blocks to be connected to each other and to the I/O pins

40. 55:032 - Introduction to Digital DesignPage 40 FPGA Structure CLB SM CLB SM CLB SM CLB SM IOB Input/Output Block Switch Matrix Configurable Logic Block

41. Page 41 FPGA CLB Structure

42. LUTs – Logic blocks are implemented using a lookup table (LUT) Small number of inputs, one output Contains storage cells that can be loaded with the desired values A 2 input LUT uses 3 MUXes to implement any desired function of 2 variables – Shannon's expansion at work! f 0/1 x 1 x 2

43. Example 2 Input LUT x1x1 x2x2 f 001 010 100 111 f = x 1 'x 2 ' + x 1 x 2, or using Shannon's expansion: f = x 1 '(x 2 ') + x 1 (x 2 ) = x 1 '(x 2 '(1) + x 2 (0)) + x 1 (x 2 '(0) + x 2 (1)) f 1 0 0 1 x 1 x 2

44. 3 Input LUT – 7 2x1 MUXes and 8 storage cells are required – Commercial LUTs have 4-5 inputs, and 16-32 storage cells f 0/1 x 2 x 3 x 1

45. Programming an FPGA – LUTs contain volatile storage cells None of the other PLD technologies are volatile FPGA storage cells are loaded via a PROM when power is first applied – The UP2 Education Board by Altera contains a JTAG port, a MAX 7000 CPLD, and a FLEX 10K FPGA The MAX 7000 CPLD chip is EPM7128SLC84-7 EPM7  MAX 7000 family; 128 macrocells; LC84  84 pin PLCC package; 7  speed grade

46. Example FPGA – Use an FPGA with 2 input LUTS to implement the function f = x 1 x 2 + x 2 'x 3 f 1 = x 1 x 2 f 2 = x 2 'x 3 f = f 1 + f 2

47. Another Example FPGA – Use an FPGA with 2 input LUTS to implement the function f = x 1 x 3 x 6 ' + x 1 x 4 x 5 x 6 ' + x 2 x 3 x 7 + x 2 x 4 x 5 x 7 Fan-in of expression is too large for FPGA (this was simple to do in a CPLD) Factor f to get sub-expressions with max fan-in = 2 – f = x 1 x 6 '(x 3 + x 4 x 5 ) + x 2 x 7 (x 3 + x 4 x 5 ) = (x 1 x 6 ' + x 2 x 7 )(x 3 + x 4 x 5 ) Could use Shannon's expansion instead – Goal is to build expressions out of 2-input LUTs

48. FPGA Implementation – f = (x 1 x 6 ' + x 2 x 7 )(x 3 + x 4 x 5 )

49. 55:032 - Introduction to Digital DesignPage 49 ALTERA FLEX 10K

50. FLEX 10K Logic array block

51. FLEX 10K Embedded Array block

52. Xilinx XC400-CLB

53. XC400 -IOB

54. Wish you all the best….. Thank you