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George Mason University ECE 448 – FPGA and ASIC Design with VHDL Survey of Reconfigurable Logic Technologies ECE 448 Lecture 17.

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Presentation on theme: "George Mason University ECE 448 – FPGA and ASIC Design with VHDL Survey of Reconfigurable Logic Technologies ECE 448 Lecture 17."— Presentation transcript:

1 George Mason University ECE 448 – FPGA and ASIC Design with VHDL Survey of Reconfigurable Logic Technologies ECE 448 Lecture 17

2 2ECE 448 – FPGA and ASIC Design with VHDL Required reading S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design Chapter 3.6 Programmable Logic Devices

3 3ECE 448 – FPGA and ASIC Design with VHDL Main source Clive „Max” Maxfield, The Design Warrior’s Guide to FPGAs Chapter 2 Fundamental Concepts Chapter 3 The Origin of FPGAs Chapter 4 Alternative FPGA Architectures

4 4ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Technology Timeline

5 5ECE 448 – FPGA and ASIC Design with VHDL Programmable Logic Devices

6 6ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) First Programmable Logic Devices

7 7ECE 448 – FPGA and ASIC Design with VHDL Programmable logic device as a black box Logic gates and programmable switches Inputs (logic variables) Outputs (logic functions)

8 8ECE 448 – FPGA and ASIC Design with VHDL General structure of a PLA (Programmable Logic Array) f 1 AND plane OR plane Input buffers & inverters P 1 P k f m x 1 x 2 x n x 1 x 1 x n x n

9 9ECE 448 – FPGA and ASIC Design with VHDL Gate-level diagram of a PLA f 1 P 1 P 2 f 2 x 1 x 2 x 3 OR plane Programmable AND plane connections P 3 P 4

10 10ECE 448 – FPGA and ASIC Design with VHDL Customary schematic for a PLA f 1 P 1 P 2 f 2 x 1 x 2 x 3 OR plane AND plane P 3 P 4

11 11ECE 448 – FPGA and ASIC Design with VHDL Programmable Array Logic f 1 P 1 P 2 f 2 x 1 x 2 x 3 AND plane P 3 P 4

12 12ECE 448 – FPGA and ASIC Design with VHDL Macrocell at the output of PAL f 1 To AND plane DQ Clock Select Enable Flip-flop

13 13ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) A generic structure of CPLD (Complex Programmable Logic Device)

14 14ECE 448 – FPGA and ASIC Design with VHDL Structure of a CPLD

15 15ECE 448 – FPGA and ASIC Design with VHDL A section of a CPLD DQ DQ DQ PAL-like block

16 16ECE 448 – FPGA and ASIC Design with VHDL Connections between the programmable interconnect matrix and simple PAL-like blocks The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

17 17ECE 448 – FPGA and ASIC Design with VHDL Field Programmable Gate Arrays

18 18ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) The world of ASICs

19 19ECE 448 – FPGA and ASIC Design with VHDL Gap between PLDs and ASICs The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

20 20ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) General structure of an FPGA

21 21ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Mux-Based Logic Block

22 22ECE 448 – FPGA and ASIC Design with VHDL LUT-Based Logic Block The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

23 23ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Xilinx Multipurpose LUT

24 24ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Simplified view of a Xilinx Logic Cell

25 25ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Xilinx CLB Slice

26 26ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Xilinx CLB

27 27ECE 448 – FPGA and ASIC Design with VHDL RAM Blocks and Multipliers in Xilinx FPGAs The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

28 28ECE 448 – FPGA and ASIC Design with VHDL Additional cores outside of the main fabric The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

29 29ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Embedded Microprocessor Cores

30 30ECE 448 – FPGA and ASIC Design with VHDL A simple clock tree The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

31 31ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Clock Manager

32 32ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Jitter

33 33ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Removing Jitter

34 34ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Frequency Synthesis

35 35ECE 448 – FPGA and ASIC Design with VHDL Figure 4-20 The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Phase shifting

36 36ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Removing Clock Skew

37 37ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) General-Purpose IO Blocks

38 38ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Using High-Speed Tranceivers to Communicate Between Devices

39 39ECE 448 – FPGA and ASIC Design with VHDL Programming Reconfigurable Logic Devices

40 40ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) A Fusible Link Technologies: Unprogrammed Device

41 41ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) A Fusible Link Technologies: Programmed Device

42 42ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) An Antifuse Technology: Unprogrammed Device

43 43ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) An Antifuse Technology: Programmed Device

44 44ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Growing an Antifuse

45 45ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) EPROM Technology

46 46ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) An EPROM Transistor-Based Memory Cell

47 47ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) EEPROM Technology

48 48ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Static RAM-based Technology

49 49ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Summary of Programming Technologies

50 50ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

51 51ECE 448 – FPGA and ASIC Design with VHDL Programming a PLD The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)

52 52ECE 448 – FPGA and ASIC Design with VHDL A PLD Programming Unit (courtesy of Data IO Corp).

53 53ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Configuration of SRAM based FPGAs

54 54ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) FPGA Configuration Modes

55 55ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Serial Load with FPGA as a Master

56 56ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Daisy-Chaining FPGAs

57 57ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Parallel Load with FPGA as a Master (off-the-shelf memory)

58 58ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Parallel Load with FPGA as a Master (special-purpose memory)

59 59ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Parallel Load with FPGA as a Slave

60 60ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Using the JTEG Port JTEG = Joint Test Action Group, IEEE

61 61ECE 448 – FPGA and ASIC Design with VHDL The Design Warrior’s Guide to FPGAs Devices, Tools, and Flows. ISBN Copyright © 2004 Mentor Graphics Corp. (www.mentor.com) Internal Processor Boundary Scan Chain

62 62ECE 448 – FPGA and ASIC Design with VHDL Reconfiguration Interfaces in Xilinx FPGAs SelectMap (8 bits Parallel) JTAG Internal Port ICAP (Virtex-II)

63 63ECE 448 – FPGA and ASIC Design with VHDL Configuration times of selected FPGA devices


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