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1 Programmable Logic

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2 Prgrammable Logic Organization Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making or breaking connections among the gates Programmable Array Block Diagram for Sum of Products Form Inputs Dense array of AND gates Product terms Dense array of OR gates Outputs

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3 Basic Programmable Logic Organizations Depending on which of the AND/OR logic arrays is programmable, we have three basic organizations AND ARRAY PROG. FIXED PROG. OR ARRAY FIXED PROG. ORGANIZATION PAL PROM PLA

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4 PLA Logic Implementation Example: Equations Personality Matrix Key to Success: Shared Product Terms 1 = asserted in term 0 = negated in term - = does not participate 1 = term connected to output 0 = no connection to output Input Side: Output Side: Reuse of terms F 3 0 1 0 0 1 F 1 1 0 1 0 0 OutputsInputsProduct term A 1 - 1 - 1 B 1 0 - 0 - C - 1 0 0 - F 0 0 0 0 1 1 F 2 1 0 0 1 0 A B B C A C B C A F0 = A + B C F1 = A C + A B F2 = B C + A B F3 = B C + A

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5 PLA Logic Implementation Example Continued – Un-programmed device All possible connections are available before programming A B C F0 F1 F2 F3

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6 PLA Logic Implementation Unwanted connections are "blown" Note: some array structures work by making connections rather than breaking them A B C F0 F1 F2 F3 AB BC AC BC A

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7 PLA Logic Implementation Alternative representation for high fan-in structures Short-hand notation so we don't have to draw all the wires! X at junction indicates a connection Notation for implementing F0 = A B + A B F1 = C D + C D A B C D AB+AB CD+CD AB CD AB Unprogrammed device Programmed device

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8 PLA Logic Implementation F1 = A B C F2 = A + B + C F3 = A B C F4 = A + B + C F5 = A B C F6 = A B C Multiple functions of A, B, C

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9 PALs and PLAs What is difference between Programmable Array Logic (PAL) and Programmable Logic Array (PLA)? PAL concept — implemented by Monolithic Memories - AND array is programmable, OR array is fixed at fabrication A given column of the OR array has access to only a subset of the possible product terms PLA concept — Both AND and OR arrays are programmable

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10 PALs and PLAs Of the two organizations the PLA is the most flexible – One PLA can implement a huge range of logic functions – BUT many pins; large package, higher cost PALs are more restricted / you trade number of OR terms vs number of outputs – Many device variations needed – Each device is cheaper than a PLA

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11 PAL Logic Implementation Design Example: BCD to Gray Code Converter Truth Table K-maps Minimized Functions: A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 W 0 0 0 0 0 1 1 1 1 1 X X X X X X X 0 0 0 0 1 1 0 0 0 0 X X X X X X Y 0 0 1 1 1 1 1 1 0 0 X X X X X X Z 0 1 1 0 0 0 0 1 1 0 X X X X X X AB CD 00011110 00 01 11 10 D B C A 00X1 01X1 01XX 0 1 XX K-map forW AB CD 00011110 00 01 11 10 D B C A 01X0 01X0 00XX 00XX K-map forX AB CD 00011110 00 01 11 10 D B C A 01X0 01 X 0 11XX 11XX K-map forY AB CD 00011110 00 01 11 10 D B C A 00X1 1 0X0 01XX 10XX K-map for Z W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D

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12 PAL Logic Implementation Minimized Functions: W = A + B D + B C X = B C Y = B + C Z = A B C D + B C D + A D + B C D

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13 PAL Logic Implementation Code Converter Discrete Gate Implementation 4 SSI Packages vs. 1 PLA/PAL Package! 1: 7404 hex inverters 2,5: 7400 quad 2-input NAND 3: 7410tri 3-input NAND 4: 7420 dual 4-input NAND

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14 Another Example: Magnitude Comparator A K-map forEQ 1000 0100 0010 0001 AB CD 00011110 00 01 11 10 D B C AB CD 00011110 00 01 11 10 D B C A 0111 0011 0000 0010 K-map forGT AB CD 00011110 00 01 11 10 D B C A 0000 1000 1101 1100 K-map forLT 0111 1011 1101 1110 AB CD 00011110 00 01 11 10 D B C K-map forNE A PLA Logic Implementation

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15 Complex Programmable Logic Devices Complex PLDs typically combine PAL combinational logic with FFs – Organized into logic blocks – Fixed OR array size – Combinational or registered output – Some pins are inputs only Usually enough logic for simple counters, state machines, decoders, etc. e.g. 22G10, 20V8, etc.

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16 Field Programmalble Gate Arrays (FPGAs) FPGAs have much more logic than CPLDs – 2K to >10M equivalent gates – Requires different architecture – FPGAs can be RAM-based or Flash-based RAM FPGAs must be programmed at power-on – External memory needed for programming data – May be dynamically reconfigured Flash FPGAs store program data in non-volitile memory – Reprogramming is more difficult – Holds configuration when power is off

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17 FPGA Structure Typical organization in 2-D array – Configurable logic blocks (CLBs) contain functional logic Combinational functions plus FFs Complexity varies by device – CLB interconnect is either local or long line CLBs have connections to local neighbors Horizontal and vertical channels use for long distance Channel intersections have switch matrix – IOBs (I/O logic Blocks) connect to pins Usually have some additional C.L./FF in block

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18 FPGA Structure CLB SM CLB SM CLB SM CLB SM IOB Input/Output Block Switch Matrix Configurable Logic Block

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