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ECE C03 Lecture 41 Lecture 4 Combinational Logic Implementation Technologies Prith Banerjee ECE C03 Advanced Digital Design Spring 1998

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ECE C03 Lecture 42 Outline Review of Combinational Logic Technologies Programmable Logic Devices (PLA, PAL) MOS Transistor Logic READING: Katz 4.1, 4.2, Dewey 5.2, 5.3, 5.4, 5.5 5.6, 5.7, 6.2

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ECE C03 Lecture 43 Programmable Arrays of Logic Gates Until now, we learned about designing Boolean functions using discrete logic gates We will now describe a technique to arrange AND and OR gates (or NAND and NOR gates) into a general array structure Specific functions can be programmed Can use programmable logic arrays (PLA) or programmable array logic (PAL)

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ECE C03 Lecture 44 PALs and PLAs Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making or breaking connections among the gates Programmable Array Block Diagram for Sum of Products Form

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ECE C03 Lecture 45 Why PALs/PLAs Work Example: F0 = A + B' C' F1 = A C' + A B F2 = B' C' + A B F3 = B' C + A Equations Personality Matrix Key to Success: Shared Product Terms 1 = asserted in term 0 = negated in term - = does not participate 1 = term connected to output 0 = no connection to output Input Side: Output Side:

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ECE C03 Lecture 46 Example of PALs and PLAs All possible connections are available before programming

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ECE C03 Lecture 47 Example of PALs and PLAs (Contd) Unwanted connections are "blown" Note: some array structures work by making connections rather than breaking them

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ECE C03 Lecture 48 Alternative Representations Short-hand notation so we don't have to draw all the wires! Notation for implementing F0 = A B + A' B' F1 = C D' + C' D

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ECE C03 Lecture 49 Design Example ABC A B C A B C F1F2F3F4F5F6 F1 = A B C F2 = A + B + C F3 = A B C F4 = A + B + C F5 = A xor B xor C F6 = A xnor B xnor C Multiple functions of A, B, C

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ECE C03 Lecture 410 Differences Between PALs and PLAs PAL concept — implemented by Monolithic Memories constrained topology of the OR Array A given column of the OR array has access to only a subset of the possible product terms PLA concept — generalized topologies in AND and OR planes

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ECE C03 Lecture 411 Design Example: BCD-to-Gray Code Converter Truth Table K-maps W = A + B D + B C X = B C' Y = B + C Z = A'B'C'D + B C D + A D' + B' C D' Minimized Functions: AB CD 00011110 00 01 11 10 D B C A 00X1 01X1 01XX 01XX K-map forW AB CD 00011110 00 01 11 10 D B C A 01X0 01X0 00XX 00XX K-map forX AB CD 00011110 00 01 11 10 D B C A 01X0 01X0 11XX 11XX K-map forY AB CD 00011110 00 01 11 10 D B C A 00X1 10X0 01XX 10XX K-map forZ

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ECE C03 Lecture 412 Programmed PAL 4 product terms per each OR gate A B C D 0 0 0 0 0 0

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ECE C03 Lecture 413 Code Converter: Discrete Gates 4 SSI Packages vs. 1 PLA/PAL Package! B \B C C A D \D D W X Y B B B B C C A D \A \C \B \B \C \A \D 2 2 1 1: 7404 hex inverters 2,5: 7400 quad 2-input NAND 3: 7410tri 3-input NAND 4: 7420 dual 4-input NAND 4 4 3 3 5 Z 1 3 2 1 2 D1 1 4 2

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ECE C03 Lecture 414 Another Example: Magnitude Comparator EQNELTGT ABCD AC BD ABD BCD ABC BCD AB CD 00011110 00 01 11 10 D B C A 1000 0100 0010 0001 K-map forEQ AB CD 00011110 00 01 11 10 D B C A 0111 1011 1101 1110 K-map forNE AB CD 00011110 00 01 11 10 D B C A 0000 1000 1101 1100 K-map forLT AB CD 00011110 00 01 11 10 D B C A 0111 0011 0000 0010 K-map forGT

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ECE C03 Lecture 415 Non-Gate Logic AND-OR-Invert PAL/PLA Generalized Building Blocks Beyond Simple Gates So far we have seen: Kinds of "Non-gate logic": switching circuits built from CMOS transmission gates multiplexer/selecter functions decoders tri-state and open collector gates read-only memories

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ECE C03 Lecture 416 Steering Logic: Switches Voltage Controlled Switches Metal Gate, Oxide, Silicon Sandwich Diffusion regions: negatively charged ions driven into Si surface Si Bulk: positively charged ions By "pulling" electrons to the surface, a conducting channel is formed "n-Channel MOS" n-type Si p-type Si

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ECE C03 Lecture 417 Switching or Steering Logic Voltage Controlled Switches Logic 0 on gate, Source and Drain connected Logic 1 on gate, Source and Drain connected

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ECE C03 Lecture 418 Logic Gates with Steering Logic Logic Gates from Switches +5V A A A B A B +5V A B A + B Inverter NAND Gate NOR Gate Pull-up network constructed from pMOS transistors Pull-down network constructed from nMOS transistors

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ECE C03 Lecture 419 Inverter with Steering Logic Inverter Operation +5V "1" "0" +5V "0" "1" Input is 1 Pull-up does not conduct Pull-down conducts Output connected to GND Input is 0 Pull-up conducts Pull-down does not conduct Output connected to VDD

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ECE C03 Lecture 420 NAND Gate with Steering Logic NAND Gate Operation A = 1, B = 1 Pull-up network does not conduct Pull-down network conducts Output node connected to GND A = 0, B = 1 Pull-up network has path to VDD Pull-down network path broken Output node connected to VDD +5V "1" "0" +5V "0" "1"

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ECE C03 Lecture 421 NOR Gate with Steering Logic NOR Gate Operation +5V "0" "1" +5V "1" "0" A = 0, B = 0 Pull-up network conducts Pull-down network broken Output node at VDD A = 1, B = 0 Pull-up network broken Pull-down network conducts Output node at GND

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ECE C03 Lecture 422 CMOS Transmission Gate nMOS transistors good at passing 0's but bad at passing 1's pMOS transistors good at passing 1's but bad at passing 0's perfect "transmission" gate places these in parallel: InOut Control InOut Control In Out Control Switches Transistors Transmission or "Butterfly" Gate

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ECE C03 Lecture 423 Selection/Demultiplexing S S I 0 I 1 S S Z Selector: Choose I0 if S = 0 Choose I1 if S = 1 S S 0 I 1 S S Z Z Demultiplexer: I to Z0 if S = 0 I to Z1 if S = 1

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ECE C03 Lecture 424 Use of Multiplexers or Demultiplexers So far, we've only seen point-to-point connections among gates Mux/Demux used to implement multiple source/multiple destination interconnect A B Z Y Multiplexers Demultiplexers A B Z Y MultiplexersDemultiplexers

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ECE C03 Lecture 425 Well-formed Switching Logic Problem with the Demux implementation: multiple outputs, but only one connected to the input! The fix: additional logic to drive every output to a known value Never allow outputs to "float" 0 I S S Z S 1 Z "0" S S S

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ECE C03 Lecture 426 Complex Steering Logic Example N Input Tally Circuit: count # of 1's in the inputs Conventional Logic for 1 Input Tally Function "0" Zero I 1 One "0" "1" Zero One "0" "1" I 1 Straight Through Diagonal Switch Logic Implementation of Tally Function

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ECE C03 Lecture 427 Complex Steering Logic Operation of the 1 Input Tally Circuit "0" Zero One "0" "1" "0" Zero One "0" "1" "0" Input is 0, straight through switches enabled

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ECE C03 Lecture 428 Complex Steering Logic Operation of 1 input Tally Circuit "0" Zero One "0" "1" Zero One "0" "1" Input = 1, diagonal switches enabled

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ECE C03 Lecture 429 Complex Steering Logic Example Extension to the 2-input case Conventional logic implementation I 1 0 0 1 1 Zero 1 0 0 0 One 0 1 1 0 Two 0 0 0 1 I 2 0 1 0 1 One I 1 I 2 Two Zero

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ECE C03 Lecture 430 Complex Steering Logic Example Switch Logic Implementation: 2-input Tally Circuit "0" Zero I 1 One "0" "1" "0" Zero One I 2 "0" Two Cascade the 1-input implementation! Zero One "0" "1" I 1 Zero One "0" I 2 Two "0"

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ECE C03 Lecture 431 Complex Steering Logic Operation of 2-input implementation Zero One "0" "1" "0" Zero One "0" "1" "0" "1" "0" "1" Zero One "0" "1" "0" Zero One "0" "1" "0" "1" "0" "1" "0" "1"

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ECE C03 Lecture 432 Summary Review of Combinational Logic Implementation Technologies Programmable Logic Devices (PLA, PAL) MOS Transistor Logic NEXT LECTURE: Combinational Logic Implementation with Multiplexers, Decoders, ROMS and FPGAs READING: Katz 4.2.2, 4.2.3, 4.2.4, 4.2.5, 10.3, Dewey 5.7

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