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111 Basic Circuit Elements n Standard TTL Small-Scale Integration: 1 chip = 2-8 gates n Requires numerous chips to build interesting circuits n Alternative:

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Presentation on theme: "111 Basic Circuit Elements n Standard TTL Small-Scale Integration: 1 chip = 2-8 gates n Requires numerous chips to build interesting circuits n Alternative:"— Presentation transcript:

1 111 Basic Circuit Elements n Standard TTL Small-Scale Integration: 1 chip = 2-8 gates n Requires numerous chips to build interesting circuits n Alternative: Complex chips for standard functions n Single chip that performs very complex computations n PALs/PLAs: Programmable for arbitrary functions n Multiplexer/Decoder/Encoder: Standard routing elements for interconnections

2 112 Programmable Logic Arrays (PLAs/PALs) Pre-fabricated building block of many AND/OR gates (or NOR, NAND) "Personalized" by making or breaking connections among the gates Programmable Array Block Diagram for Sum of Products Form

3 113 Benefits of PLAs Example: F0 = A + B C F1 = A C + A B F2 = B C + A B F3 = B C + A Equations Personality Matrix Key to Success: Shared Product Terms 1 = asserted in term 0 = negated in term - = does not participate 1 = term connected to output 0 = no connection to output Input Side: Output Side:

4 114 Unprogrammed PLA All possible connections are available before programming

5 115 Programmed PLA Unwanted connections are "blown"

6 116 Simplified PLA Diagrams Short-hand notation so we don't have to draw all the wires! Notation for implementing F0 = A B + A' B' F1 = C D' + C' D

7 117 PLA Example F1 = A B C F2 = A + B + C F3 = A B C F4 = A + B + C F5 = A xor B xor C F6 = A xor B xor C Multiple functions of A, B, C F1F2F3F4F5F6

8 118 PALs vs. PLAs What is difference between Programmable Array Logic (PAL) and Programmable Logic Array (PLA)? PAL concept: constrained topology of the OR Array A given column of the OR array has access to only a subset of the possible product terms PLA concept — generalized topologies in AND and OR planes

9 119 PAL Example X = BCD + ABCD + AD Y = CD + AB + ACD + BCD

10 120 PLA Design Example: 2’s Comp. Compare AB CD D B C A K-map forGT AB CD D B C A K-map forLT AB CD D B C A K-map forNE AB CD D B C A K-map forEQ NELTGT

11 121 Design Example: Basic Telephone System n Put together a simple telephone system D/A A/D Ear Mouth Bell Start EMBSEMBS

12 122 Basic Telephone System (cont.) n Multiple subscribers, one operator. n Operator controls all connections EMBSEMBS EMBSEMBS EMBSEMBS EMBSEMBS EMBSEMBS Operator

13 123 Standard Circuit Elements n Develop implementations of important “Building Blocks” n Used in Networks, Computers, Stereos, etc. n Multiplexer: Combine N sources onto 1 wire n Decoder: Determine which input is active n Encoder: Convert binary to one-of-N wires

14 124 Decoders n Used to select one of 2 N outputs based on N input bits n Input: N bits; output: 2 N outputs -- only one is active n A decoder that has n inputs and m outputs is referred to as an n x m, N:M, or n-to-m decoder n Example: 3-to-8 decoder 3:8 dec ABC S 2 S 1 S 0 D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7

15 125 Decoder Implementation

16 126 Enabled Decoder Implementation n Active High enable

17 127 Decoder Expansion n Construct a 4:16 decoder using 2:4 decoders

18 128 Decoders in General Logic Implementation n Implement F = WXZ + XZ w/4x16 Decoder S 3 S 2 S 1 S 0 4:16 dec En

19 129 Encoders n Performs the inverse operation of decoders n Input: 2 N or less lines -- only 1 is asserted at any given time n Output: N output lines n Function: the output is the binary representation of the ID of the input line that is asserted

20 130 Encoder Implementation n 4:2 Encoder

21 131 Priority Encoder n Use priorities to resolve the problem of 2 or more input lines active at a time. n One scheme: Highest ID active wins n Also add an output to identify when at least 1 input active

22 132 Priority Encoder Implementation

23 133 Priority Encoder Implementation (cont.)

24 134 Multiplexer n An element that selects data from one of many input lines and directs it to a single output line n Input: 2 N input lines and N selection lines n Output: the data from one selected input line n Multiplexer often abbreviated as MUX

25 135 Multiplexer Implementation n 4:1 MUX

26 136 Multiplexer Expansion n Construct a 16:1 MUX using 4:1 MUX’s

27 137 Multiplexers in General Logic n Implement F = XYZ + YZ with a 8:1 MUX 8:1 MUX S2 S1 S0 F

28 138 Multiplexers in General Logic (cont.) n Implement F = XYZ + YZ with a 4:1 MUX S1 S0 4:1 MUX F


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