2 Prgrammable Logic Organization Pre-fabricated building block of many AND/OR gates (or NOR, NAND)"Personalized" by making or breaking connections among the gatesInputsDense array ofAND gatesDense array ofOR gatesProducttermsOutputsProgrammable Array Block Diagram for Sum of Products Form
3 Basic Programmable Logic Organizations Depending on which of the AND/OR logic arrays is programmable, we have three basic organizationsAND ARRAYPROG.FIXEDOR ARRAYORGANIZATIONPALPROMPLA
4 PLA Logic Implementation Key to Success: Shared Product TermsEquationsF0 = A + B CF1 = A C + A BF2 = B C + A BF3 = B C + AExample:Personality MatrixInput Side:F1OutputsInputsProducttermA-BC23A BB CA C1 = asserted in term0 = negated in term- = does not participateReuseoftermsOutput Side:1 = term connected to output0 = no connection to output
5 PLA Logic Implementation Example Continued - Unprogrammed deviceABCF0F1F2F3All possible connections are availablebefore programming
6 PLA Logic Implementation Example Continued -Programmed partABCF0F1F2F3ABBCACUnwanted connections are "blown"Note: some array structureswork by making connectionsrather than breaking them
7 PLA Logic Implementation Unprogrammed deviceAlternative representationShort-hand notationso we don't have todraw all the wires!X at junction indicatesa connectionA B C DAB+ABCD+CDABCDNotation for implementingF0 = A B + A BF1 = C D + C DProgrammed device
8 PLA Logic Implementation ABCABCF1F2F3F4F5F6Design ExampleMultiple functions of A, B, CF1 = A B CF2 = A + B + CF3 = A B CF4 = A + B + CF5 = A B CF6 = A B C
9 PALs and PLAsWhat is difference between Programmable Array Logic (PAL) andProgrammable Logic Array (PLA)?PAL concept — implemented by Monolithic MemoriesAND array is programmable, OR array is fixed at fabricationA given column of the OR arrayhas access to only a subset ofthe possible product termsPLA concept — Both AND and OR arrays are programmable
10 PALs and PLAs Of the two organizations the PLA is the most flexible One PLA can implement a huge range of logic functionsBUT many pins; large package, higher costPALs are more restricted / you trade number of OR terms vs number of outputsMany device variations neededEach device is cheaper than a PLA
11 PAL Logic Implementation Design Example: BCD to Gray Code ConverterK-mapsTruth TableABCD00011110DBCAX1K-map forWYZA1BCDWXYZMinimized Functions:W = A + B D + B CX = B CY = B + CZ = A B C D + B C D + A D + B C D
12 PAL Logic Implementation Programmed PAL:A B C DA B C DABDBCBCBCDADW X Y ZMinimized Functions:W = A + B D + B CX = B CY = B + CZ = A B C D + B C D + A D + B C D4 product terms per each OR gate
14 PLA Logic Implementation Another Example: Magnitude ComparatorEQNELTGTABCDACBDABDBCDABCA B C DAK-map forEQ1ABCD00011110DBCGTLTNE
15 Another Variation: Synchronous vs. Asynchronous Outputs DQQ0Q1OpenComSeqCLKNReset
16 Complex Programmable Logic Devices Complex PLDs typically combine PAL combinational logic with FFsOrganized into logic blocksFixed OR array sizeCombinational or registered outputSome pins are inputs onlyUsually enough logic for simple counters, state machines, decoders, etc.e.g. GAL22V10, GAL16V8, etc.
17 GAL CPLDOLMC (Output Logic MacroCell) has OR, FF, output multiplexer and I/O control logic.Note that OLMC output is fed back to input matrix for use in other OLMCs.
19 PAL22V10 OLMC Configuration Modes Registered Mode: active (low, high): Q’ is feedback as input only, no dedicated input in this modeCombinational Mode: active (low, high) can feedback comb. Output (high, low) and/or dedicated input
20 GAL16V8 OLMC Structure 11 10 01 00 T S M U X O 1 P F 10- 11- 0-1 0-0 D QvccXOR(n)FROMANDARRAYFEEDBACKCLKOEI/O(n)ADJ. STAGEOUTPUT(m)AC0AC1(n)ACOAC1(m)
21 PAL16V8 OLMC Configuration Modes Simple mode (combinational output)combinational outputcombinational output with feedbackdedicated inputComplex modecombinational output, with feedbackcombinational input from another OLMC Registered mode: active (low, high): Q’ is feedback as input (no dedicated input)
22 Field Programmable Gate Arrays (FPGAs) FPGAs have much more logic than CPLDs2K to >10M equivalent gatesRequires different architectureFPGAs can be RAM-based or Flash-basedRAM FPGAs must be programmed at power-onExternal memory needed for programming dataMay be dynamically reconfiguredFlash FPGAs store program data in non-volatile memoryReprogramming is more difficultHolds configuration when power is off
23 FPGA Structure Typical organization in 2-D array Configurable logic blocks (CLBs) contain functional logic (could be similar to PAL22V10)Combinational functions plus FFsComplexity varies by deviceCLB interconnect is either local or long lineCLBs have connections to local neighborsHorizontal and vertical channels use for long distanceChannel intersections have switch matrixIOBs (I/O logic Blocks) connect to pinsUsually have some additional C.L./FF in block
24 Field-Programmable Gate Arrays structure Logic blocksTo implement combinational and sequential logicInterconnectWires to connect inputs and outputs to logic blocksI/O blocksSpecial logic blocks at periphery of device for external connectionsKey questions:How to make logic blocks programmable?How to connect the wires?After the chip has been fabbedHW problems: 7-19, 7-20, 7-22, 7-23, 7-26 due 22/9/07
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