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ECE C03 Lecture 151 Lecture 15 Finite State Machine Implementation Prith Banerjee ECE C03 Advanced Digital Design Spring 1998.

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Presentation on theme: "ECE C03 Lecture 151 Lecture 15 Finite State Machine Implementation Prith Banerjee ECE C03 Advanced Digital Design Spring 1998."— Presentation transcript:

1 ECE C03 Lecture 151 Lecture 15 Finite State Machine Implementation Prith Banerjee ECE C03 Advanced Digital Design Spring 1998

2 ECE C03 Lecture 152 Outline Mapping FSM to random logic Mapping FSM to ROMS Mapping FSM to PLAs Mapping FSM to Programmable Logic Devices (Xilinx) READING: Katz , , 10.3, Dewey 9.5

3 ECE C03 Lecture 153 FSM Implementation Strategies Discrete Gate Logic Emphasis so far MSI Logic (e.g., Counters) Structured Logic (e.g., PLA/PAL, ROM) Field Programmable Gate Arrays (FPGAs) Function can be configured "on the fly" or in the field Flipflops/Registers plus discrete gates on the same chip

4 ECE C03 Lecture 154 FSM Design with Structured Logic Block Diagram for Synchronous Mealy Machine Block Diagram for Synchronous Mealy Machine ROM-based Realization Inputs & Current State form the address ROM data bits form the Outputs & Next State

5 ECE C03 Lecture 155 ROM-Based Implementation Example: BCD to Excess 3 Serial Converter BCD Excess 3 Code Conversion Process Bits are presented in bit serial fashion starting with the least significant bit Single input X, single output Z

6 ECE C03 Lecture 156 BCD to Excess-3 Converter State Transition Table Derived State Diagram Reset S0 0/11/0 S1 0/1 1/0 S2 0/0, 1/1 S3 0/0, 1/1 S4 1/0 0/1 S5 0/0, 1/1 S6 0/1

7 ECE C03 Lecture 157 ROM-Based Implementation BCD to Excess 3 Converter Truth Table/ROM I/Os Circuit Level Realization = 4 x positive edge triggered D FFs In ROM-based designs, no need to consider state assignment QA QB QC QD CLK CLR 1 converter ROM X Q2 Q1 Q0 Z D2 D1 D D C B A CLK \Reset X Z 9 5 4

8 ECE C03 Lecture 158 ROM Based Implementation BCD to Excess-3 Converter Timing Behavior for input strings (0) and (7) LSBMSB LSB

9 ECE C03 Lecture 159 PLA Based Design BCD to Excess 3 Converter State Assignment with NOVA S0 = 000 S1 = 001 S2 = 011 S3 = 110 S4 = 100 S5 = 111 S6 = 101 NOVA derived state assignment 9 product term implementation 0 S0 S1 1 1 S0 S2 0 0 S1 S3 1 1 S1 S4 0 0 S2 S4 0 1 S2 S4 1 0 S3 S5 0 1 S3 S5 1 0 S4 S5 1 1 S4 S6 0 0 S5 S0 0 1 S5 S0 1 0 S6 S0 1 NOVA input file

10 ECE C03 Lecture 1510 PLA Implementation BCD to Excess 3 Converter Espresso Inputs Espresso Outputs.i 4.o 4.ilb x q2 q1 q0.ob d2 d1 d0 z.p e.i 4.o 4.ilb x q2 q1 q0.ob d2 d1 d0 z.p e

11 ECE C03 Lecture 1511 PLA Implementation BCD to Excess 3 Converter D2 = Q2 Q0 + Q2 Q0 D1 = X Q2 Q1 Q0 + X Q2 Q0 + X Q2 Q0 + Q1 Q0 D0 = Q0 Z = X Q1 + X Q1

12 ECE C03 Lecture 1512 PAL Implementation BCD to Excess 3 Serial Converter 10H8 PAL: 10 inputs, 8 outputs, 2 product terms per OR gate D1 = D11 + D12 D11 = X Q2 Q1 Q0 + X Q2 Q0 D12 = X Q2 Q0 + Q1 Q0 0. Q2 Q0 1. Q2 Q0 8. X Q2 Q1 Q0 9. X Q2 Q0 16. X Q2 Q0 17. Q1 Q0 24. D D Q0 33. not used 40. X Q1 41. X Q1

13 ECE C03 Lecture 1513 PAL Implementation BCD to Excess 3 Serial Converter

14 ECE C03 Lecture 1514 More Advanced PAL Architectures Registered PAL Architecture Buffered Input or product term Negative Logic Feedback D2 = Q2 Q0 + Q2 Q0 D1 = X Q2 Q1 Q0 + X Q2 + X Q0 + Q2 Q0 + Q1 Q0 D0 = Q0 Z = X Q1 + X Q1

15 ECE C03 Lecture 1515 Advanced PAL Architectures Programmable Output Polarity/XOR PALs Buried Registers: decouple FF from the output pin Advantage of XOR PALs: Parity and Arithmetic Operations

16 ECE C03 Lecture 1516 Examples of XOR and Registered PALs Example of XOR PAL Example of Registered PAL

17 ECE C03 Lecture 1517 FSM Design With Counters Synchronous Counters: CLR, LD, CNT Four kinds of transitions for each state: (1) to State 0 (CLR) (2) to next state in sequence (CNT) (3) to arbitrary next state (LD) (4) loop in current state Careful state assignment is needed to reflect basic sequencing of the counter Careful state assignment is needed to reflect basic sequencing of the counter

18 ECE C03 Lecture 1518 Implementation Strategies FSM Design with Counters Excess 3 Converter Revisited Note the sequential nature of the state assignments

19 ECE C03 Lecture 1519 Implementation Strategies FSM Design with Counters Excess 3 Converter CLR signal dominates LD which dominates Count

20 ECE C03 Lecture 1520 Implementation FSM With Counters Excess 3 Converter Espresso Input File Espresso Output File.i 5.o 7.ilb res x q2 q1 q0.ob z clr ld en c b a.p e.i 5.o 7.ilb res x q2 q1 q0.ob z clr ld en c b a.p e

21 ECE C03 Lecture 1521 Implementing FSM with Counters Excess 3 Converter Schematic Synchronous Output Register

22 ECE C03 Lecture 1522 FSM Design with FPGAs Programmable Logic Devices = PLD Field Programmable Gate Arrays = FPGAs Altera MAX Family Actel Programmable Gate Array Xilinx Logical Cell Array PALs, PLAs = Gate Equivalents (s) of Gate Equivalents!

23 ECE C03 Lecture 1523 Xilinx Logic Cell Arrays CMOS Static RAM Technology: programmable on the fly! All personality elements connected into serial shift register Shift in string of 1's and 0's on power up General Chip Architecture: Logic Blocks (CLBs) IO Blocks (IOBs) Wiring Channels

24 ECE C03 Lecture 1524 Xilinx LCA Architecture Inputs: Tri-state enable bit to output input, output clocks Outputs: input bit Internal FFs for input & output paths Fast/Slow outputs 5 ns vs. 30 ns rise Pull-up used with unused IOBs

25 ECE C03 Lecture 1525 Xilinx LCA Architecture Configurable Logic Block: CLB 2 FFs Any function of 5 Variables Global Reset Clock, Clock Enb Independent DIN

26 ECE C03 Lecture 1526 Xilinx CLB Function Generator CLB Function Generator Any function of 5 variables Two Independent Functions of 4 variables each

27 ECE C03 Lecture 1527 Xilinx CLB Function Generator Certain Limited Functions of 6 Variables

28 ECE C03 Lecture 1528 Xilinx Interconnect Architecture Interconnect Direct Connections Global Long Line Horizontal/Vertical Long Lines Switching Matrix Connections

29 ECE C03 Lecture 1529 Implementing FSM with Xilinx LCA Implementing the BCD to Excess 3 FSM Q2+ = Q2 Q0 + Q2 Q0 Q1+ = X Q2 Q1 Q0 + X Q2 Q0 + X Q2 Q0 + Q1 Q0 Q0+ = Q0 Z = Z Q1 + X Q1 No function more complex than 4 variables 4 FFs implies 2 CLBs Synchronous Mealy Machine Global Reset to be used Place Q2+, Q0+ in once CLB Q1, Z in second CLB maximize use of direct & general purpose interconnections

30 ECE C03 Lecture 1530 Implementing FSM with Xilinx LCA Implementing the BCD to Excess 3 FSM

31 ECE C03 Lecture 1531 Summary Mapping FSM to random logic Mapping FSM to ROMS Mapping FSM to PLAs Mapping FSM to Programmable Logic Devices (Xilinx) NEXT LECTURE: VHDL Language READING: Dewey 11.2, 11.3, 11.4, 11.5, 11.6, 12.2, 12.2


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