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1 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Configurations Read Only Memory (ROM) – –a fixed array of AND gates and a programmable array of OR gates Programmable Array Logic (PAL) – –a programmable array of AND gates feeding a fixed array of OR gates. Programmable Logic Array (PLA) – – a programmable array of AND gates feeding a programmable array of OR gates. Complex Programmable Logic Device (CPLD) /Field- Programmable Gate Array (FPGA) – –complex enough to be called “architectures”

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2 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 ROM, PAL and PLA Configurations (a) Programmable read-only memory (PROM) Inputs Fixed AND array (decoder) Programmable OR array Outputs Programmable Connections (b) Programmable array logic (PAL) device Inputs Programmable AND array Fixed OR array Outputs Programmable Connections (c) Programmable logic array (PLA) device Inputs Programmable OR array Outputs Programmable Connections Programmable Connections Programmable AND array

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3 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Read Only Memory Read Only Memories (ROM) or Programmable Read Only Memories (PROM) have: –N input lines, –M output lines, and –2 N decoded minterms. Fixed AND array with 2 N outputs implementing all N-literal minterms. Programmable OR Array with M outputs lines to form up to M sum of minterm expressions. A program for a ROM or PROM is simply a multiple-output truth table –If a 1 entry, a connection is made to the corresponding minterm for the corresponding output –If a 0, no connection is made

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4 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Example: A 8 X 4 ROM (N = 3 input lines, M= 4 output lines) The fixed "AND" array is a “decoder” with 3 inputs and 8 outputs implementing minterms. The programmable "OR“ array uses a single line to represent all inputs to an OR gate. An “X” in the array corresponds to attaching the minterm to the OR Read Example: For input (A 2,A 1,A 0 ) = 011, output is (F 3,F 2,F 1,F 0 ) = What are functions F 3, F 2, F 1 and F 0 in terms of (A 2, A 1, A 0 )? Read Only Memory Example D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 A B C F0 F1F2 F3 X X X X X X X X X X

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5 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Array Logic (PAL) The PAL is the opposite of the ROM, having a programmable set of ANDs combined with fixed ORs. Disadvantage –ROM guaranteed to implement any M functions of N inputs. PAL may have too few inputs to the OR gates. Advantages –For given internal complexity, a PAL can have larger N and M –Some PALs have outputs that can be complemented, adding POS functions –No multilevel circuit implementations in ROM (without external connections from output to input). PAL has outputs from OR terms as internal inputs to all AND terms, making implementation of multi-level circuits easier.

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6 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Array Logic Example 4-input, 3-output PAL with fixed, 3-input OR terms What are the equations for F1 through F4? F1 = C’ + A’B’ F2 = A’BC’ + AC + AB’ F3 = AD + BD + F1 F4 = AB + CD + F1’ AND gates inputs 09 Product term F 1 F 2 F 3 F 4 I 3 = C I 2 = B I 1 = A I 4 = D X X XX X XX X X X X X XX X X X X X X

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7 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 P rogrammable Logic Array (PLA ) Compared to a ROM and a PAL, a PLA is the most flexible having a programmable set of ANDs combined with a programmable set of ORs. Advantages –A PLA can have large N and M permitting implementation of equations that are impractical for a ROM (because of the number of inputs, N, required –A PLA has all of its product terms connectable to all outputs, overcoming the problem of the limited inputs to the PAL ORs –Some PLAs have outputs that can be complemented, adding POS functions Disadvantage –Often, the product term count limits the application of a PLA. Two-level multiple-output optimization reduces the number of product terms in an implementation, helping to fit it into a PLA.

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8 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Logic Array Example 3-input, 3-output PLA with 4 product terms What are the equations for F 1 and F 2 ? Could the PLA implement the functions without the XOR gates? Fuse intact Fuse blown 1 F 1 F 2 X A B C CCBBAA X X X X X X X X X X X X X X A B A C B C A B X

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9 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Combinational Functions and Circuits Rudimentary logic functions Decoding Encoding Selecting

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10 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Rudimentary Logic Functions Functions of a single variable X Can be used on the inputs to functional blocks to implement other than the block’s intended function 0 1 F= 0 F= 1 (a) F= 0 F= 1 V CC or V DD (b) XF= X (c) XF= X (d)

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11 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Multiple-bit Rudimentary Functions Multi-bit Examples: A wide line is used to represent a bus which is a vector signal In (b) of the example, F = (F 3, F 2, F 1, F 0 ) is a bus. The bus can be split into individual bits as shown in (b) Sets of bits can be split from the bus as shown in (c) for bits 2 and 1 of F. The sets of bits need not be continuous as shown in (d) for bits 3, 1, and 0 of F. F (d) 0 F 3 1 F 2 F 1 A F 0 (a) 0 1 A F 0 (b) 4 2:1 F(2:1) 2 F (c) 4 3,1:0 F(3), F(1:0) 3 A A

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12 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Enabling Function Enabling permits an input signal to pass through to an output Disabling blocks an input signal from passing through to an output, replacing it with a fixed value The value on the output when it is disable can be Hi-Z (as for three-state buffers and transmission gates), 0, or 1 When disabled, 0 output When disabled, 1 output

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13 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Decoders Multiple-input multiple-output logic circuit which maps coded inputs to coded outputs n input bits can code upto 2 n different output bits n-to-m decoder: maps n-bit input to m-bit output where m < 2 n

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14 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Decoders General decoder structure Typically n inputs, 2 n outputs –2-to-4, 3-to-8, 4-to-16, etc.

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15 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Binary 2-to-4 decoder Note “x” (don’t care) notation.

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16 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 2-to-4-decoder logic diagram m 0 =I1’I0’ m 1 =I1’I0 m 2 =I1I0’ m 3 =I1I0

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17 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Decoder Expansion 3-to-8 decoder out of 2 2-to-4 decoders with enable

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18 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Decoder and OR Gate Implementation of a Binary Adder Arithmetic sum of three bits X,Y,Z Output pair (C,S) S(X,Y,Z) = C(X,Y,Z) =

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19 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 S(X,Y,Z) = C(X,Y,Z) =

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20 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Decoder Applications Microprocessor memory systems –Selecting different banks of memory Microprocessor input/output systems –Selecting different devices Microprocessor instruction decoding –Enabling different functional units Memory chips –Enabling different rows of memory depending on address Lots of other applications –Seven segment decoder, 4-to-7 decoder

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21 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Encoders vs. Decoders DecoderEncoder

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22 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Binary encoders

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23 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Need priority in most applications

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24 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Priority Encoder

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25 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 A 0 = D 3 + D 1 D 2 ’ A 1 = D 2 + D 3 V = D 0 + D 1 + D 2 + D 3

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26 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Another approach to the design of 8-input priority encoder

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27 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Priority-encoder logic equations

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28 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Selecting of data or information is a critical function in digital systems and computers Circuits that perform selecting have: –A set of information inputs from which the selection is made –A single output –A set of control lines for making the selection Logic circuits that perform selecting are called multiplexers Selecting can also be done by three-state logic or transmission gates Selecting

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29 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Multiplexers MUX: –Selects binary information from one of many input lines and directs the information to a single output line. –Selection of a particular input is controlled by a set of input variables. –# of selection control bits: n –# of possible input lines: 2 n –# of output: 1 2 n -to-1 MUX

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30 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Multiplexers

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31 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 4-to-1-Line MUX

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32 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Quadruple 2-to-1-Line MUX

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33 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Combinational Circuit Implementation Using MUX F(X,Y,Z)= m(1,2,6,7) using a 4-to-1 MUX

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34 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 F(A,B,C,D)= m(1,3,4,11,12,13,14,15)

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35 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Demultiplexer Inverse of the MUX Receives information from a single line and transmits it to one of the 2 n possible output lines 1-to-4-Line DMUX / 2-to-4-Line Decoder

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36 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Binary Adders Arithmetic circuits: –combinational circuits with add, subt, mult & div. Present a hierarchical design –Simple addition of two bits 0+0 = 0 2, 0+1 = 1 2, 1+0 = 1 2 and 1+1 = 10 2 –Half Adder: Combinational circuit that adds two bits –Full Adder: Combinational circuit that adds three bits (two input, one carry)

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37 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Half Adder Sum of two binary digits S=X’Y+XY’ C=XY

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38 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Full Adder Sum of three binary digits

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39 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Logic Diagram for Full Adder XY Z(X Y) XY + Z(X Y) X Y Z

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40 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Binary Ripple Carry Adder The parallel adder of n binary full adders Carry out Carry in of next full adder

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41 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Carry Lookahead Adder Ripple carry adder –Simple but has a long circuit delay Define a partial full adder Try to lower gate delays for ripple carry adder

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42 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Binary Adder/Subtractor

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43 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Overflow When does it occur? How do we detect it? ? ? 10110

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44 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Binary Multipliers

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45 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 4-bit by 3-bit multiplier

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