Presentation on theme: "Digital Design: Combinational Logic Blocks"— Presentation transcript:
1 Digital Design: Combinational Logic Blocks Credits:Slides adapted from:J.F. Wakerly, Digital Design, 4/e, Prentice Hall, 2006C.H. Roth, Fundamentals of Logic Design, 5/e, Thomson, 2004A.B. Marcovitz, Intro. to Logic and Computer Design, McGraw Hill, 2008R.H. Katz, G. Borriello, Contemporary Logic Design, 2/e, Prentice-Hall, 2005
2 Multiplexers (Data Selectors) A multiplexer (MUX for short) is a digital switch:it passes (connects) one of its data inputs to the output.the data input selected is a function of a set of control inputs called selection inputs.I1 I0 A ZA Z 0 I0 1 I1Two alternative formsfor a 2:1 Mux truth tableZ = A' I0 + A I1
5 Cascading multiplexers Large multiplexers can be made by cascading smaller onesI0 I1 I2 I3I4 I5 I6 I74:1 mux2:1 mux8:1 muxalternative implementation4:1 mux2:1 muxI4 I5I2 I3I0 I1I6 I78:1 muxZZB CAControl signals B and C simultaneously choose one of I0, I1, I2, I3 and one of I4, I5, I6, I7Control signal A chooses which of the upper or lower mux's output to gate to ZCA B
6 Multiplexers as general-purpose logic A 2n:1 multiplexer can implement any function of n variableswith the variables used as control inputs andthe data inputs tied to 0 or 1Example:F(A,B,C) = m0 + m2 + m6 + m = A'B'C' + A'BC' + ABC' + ABCFCABS28:1 MUXS1S0Z= A'B'C'(1) + A'B'C(0) + A'BC'(1) + A'BC(0) +AB'C'(0) + AB'C(0) + ABC'(1) + ABC(1)Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7
7 Multiplexers as general-purpose logic (cont’d) Generalization data inputs can also be tied to variables not just 0’s an 1’sI0 I In-1 In F In In' 1four possibleconfigurations of truth table rows can be expressed as a function of Inn-1 mux control variablessingle mux data variable
8 Activity Realize F = B’CD’ + ABC’ with a 4:1 multiplexer 0 when B’C’ A B C D Z0 when B’C’D’ when B’CA when BC’0 when BCBCS1S0F4:1 MUX0 D’ A 0Z = B’C’(0) + B’C(D’) + BC’(A) + BC(0)
10 DemultiplexersRoute a single input to one of many outputs, as a function of a set of control inputs3xy0y1y2y3y4y5y6y7s[2:0]1:8demux
11 Three-State BuffersNormally, a logic circuit will not operate correctly if the outputs of two or more gates or other logic devices are directly connected to each other (multiple drivers conflict).Use of tri-state logic permits the outputs of two or more gates or other logic devices to be connected together1B1?The two driving blocks fightwith each otherB2(buffers are a.k.a. drivers)
12 Tri-state Buffers (cont’d) When the enable B is 1, the output C equals A.When the enable B is 0, the output C acts like an open circuit.In this case the output C is effectively disconnected from thebuffer output so that no current can flow.This is often referred as Hi-Z (high-impedance) state becausethe circuit offers a very high impedance to the flow of current.
17 DecodersA decoder is a logic circuit that converts coded inputs into coded outputs.Each input code word produces a different output code word (there is a one-to-one mapping between inputs and outputs)
23 Decoders as general-purpose logic n-to-2n decoders can implement any function of n variableswith the variables used as control inputsthe appropriate minterms summed to form the functiondecoder generates appropriateminterm based on control signals(it "decodes" control signals)A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABCCABS23:8 DECS1S0
29 Read-Only Memories (ROM) A ROM consists of a two dimensional array of semiconductor devices interconnected to store an array of binary dataTwo-level canonical form combinational logic can be implemented using a ROM as a look-up-table (LUT)truth tableA B C F0 F1 F2 F3F0 = A' B' C + A B' C' + A B' CF1 = A' B' C + A' B C' + A B CF2 = A' B' C' + A' B' C + A B' C'F3 = A' B C + A B' C' + A B C'
32 PLA (Programmable Logic Arrays) A PLA performs the same basic LUT task as a ROM.A PLA with n inputs and m outputs can realize m combinational functions of n variables.The internal organization of a PLA is different from that of the ROM
35 Activity Map the following functions to the PLA below: W = AB + A’C’ + BC’X = ABC + AB’ + A’BY = ABC’ + BC + B’C’ABCWXY
36 Activity (cont’d) 9 terms won’t fit in a 7 term PLA Manipulating logic functionsso that they can use availableresources is calledTechnology Mapping9 terms won’t fit in a 7 term PLAcan apply concensus theorem to W to simplify to: W = AB + A’C’8 terms wont’ fit in a 7 term PLAobserve that AB = ABC + ABC’can rewrite W to reuse terms: W = ABC + ABC’ + A’C’Now it fitsW = ABC + ABC’ + A’C’X = ABC + AB’ + A’BY = ABC’ + BC + B’C’ABCWXYABCABC’A’C’AB’A’BBCB’C’
37 PAL (Programmable Array Logic) The PAL is a special case of the PLA in which the AND array is programmable and the OR array is fixedFigure. PAL Segment
39 CPLDs and FPGAs The distinction between CPLD and FPGAs is blurred. CPLDs contain a matrix of logic macrocells that usually consist of programmable array logic followedby a flip-flop or latch. The macrocells are connectedusing a single large programmable interconnect blockFPGAs contain a regularstructure of programmable basiclogic cells surrounded byprogrammable interconnect.