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ITRS Meeting. Stresa, Italy. April 19-20, 2004. G. Bomchil. ST Microelectronics 1 Integrated Project « CMOS backbone for 2010 e-Europe » NANOCMOS From.

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Presentation on theme: "ITRS Meeting. Stresa, Italy. April 19-20, 2004. G. Bomchil. ST Microelectronics 1 Integrated Project « CMOS backbone for 2010 e-Europe » NANOCMOS From."— Presentation transcript:

1 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 1 Integrated Project « CMOS backbone for 2010 e-Europe » NANOCMOS From the 45 nm node down to the limits

2 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 2 OUTLINE European context Project objectives Consortium Project Structure Details of the work program Conclusions

3 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 3 N ANO C MOS European Context q Integrate in a coherent structure Cooperative European R§D projects and in the field of NANOCMOS Integrated Circuits. Make a substantial contribution to optimize European efforts in Microelectronics in particular between Frame Work Programme 6 Information Society Technology (IST) projects funded by the European Commission and MEDEA+ projects funded through the EUREKA mechanism.

4 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 4 ADEQUAT m FE; 0.35 m BE ADEQUAT m FE; 0.35 m BE 0.18 m FE; 0.25 m BE ACE m FE; 0.18 m BE HUNT ARTEMIS65 nm FE N ANOCMOS IST: 45 nm FE; 45 nm BE, 32/22, MEDEA: 45 nm Full Integr ADEQUAT + COIN ADEQUAT DAMASCENECopper inter. 100 nm FE MEDEA T20190 nm Full Integr NESTOR ULISSECu/low k 45/32/22 FE MEDEA T20765 nm Full Integr. European Technology Projects

5 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 5 N ANO C MOS 45 nm demonstration of feasibility 32/22 nm anticipation (European Commission) N ANO C MOS 45 nm CMOS-300 Full CMOS Process Integration (MEDEA+) NEO: SINANO STREPS

6 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 6 NANOCMOS TECHNICAL OBJECTIVES Achieve a demonstration of feasibility of a 45 nm CMOS logic process Q3/Q4 2005(IST Project) and a first full CMOS integration in a 300 mm industrial facility in 2007 (MEDEA+ project). NANOCMOS planning allows time for further work to achieve maturity of a 45nm industrial process. Fits with 2003 ITRS Roadmap predictions/criteria for the 45 nm node product shipment in Start the R§D activities on materials and process for a demonstration of feasibility of a 32 nm CMOS logic process in Start the R§D activities on materials and process aiming the 22 nm node, in close cooperation with a Network of Excellence (SINANO) gathering more 50 European Universities /Institutes research teams.

7 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 7 INITIAL CONSORTIUM IC MANUFACTURERS ST Microelectronics Crolles § Agrate(F, I), PHILIPS Semiconductors Crolles(F), INFINEON(D) RESEARCH INSTITUTES § ACADEMIC TEAMS IMEC(B), CEA-LETI(F), PHILIPS Research Leuven(B) § Eindhoven(NTH) FHG(D, three centers), CNRS(F, eight laboratories), ZFM/TU Chemnitz(D) SMEs IBS(F), ISILTEC(D), MAGWELL(B), ACIES(F)

8 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 8 PROJECT STRUCTURE

9 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 9 SUB PROJECT I: MATERIALS q WP I.1.1: Strained buffer layers Thin SRBs (IMEC) Relaxation mechanisms starting from pure Ge (CNRS, LETI) STI process for SRBs (IMEC) Strained Si on SRB: CMP, cleaning, doping, thermal stability (ST) Integration(ST) q WP I.1.2: Strained Si on SiGeC Epi re-growth of SiGeC with different C concentration (CNRS/IEF) Growth of SiGeC with high C concentration gradient (ST, LETI) q WP I.1.3:Evaluation and characterization strained Si and relaxed SiGe Identification and characterization of crystal defects (CNRS) q WP I.2.1: SOI for high mobility materials (LETI) Growth of SiGeC on very thin SOI q WP I.1.2: Strained Si on SOI (IMEC) Growth of ultra thin SRB on SOI (Ge condensation)

10 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 10 SUB PROJECT II: FEOL MODULES WP II.1.1 High-k gate dielectrics (ST, LETI, FhG, IMEC, PHILIPS) HfO2 and silicates based dielectrics by ALCVD and MOCVD Interface, cleaning Perovskite dielectrics formed by MBE(CNRS) High-k formation via ion implantation (IBS) WP II.1.2 Metal gate electrodes MOCVD metal, ALD nitride based, PVD TaN (ST, LETI, IMEC, PHILIPS) Dry etching (CNRS) WP II.1.3 Surface preparation (IMEC, LETI) WP II.2.1 S/D extensions Low Rsq, <15 nm junctions: SPER, LTA (ST, LETI, IMEC, PHILIPS, CNRS) Plasma immersion implantation (IBS) WP II.2.2 Silicides and elevated source-drain Scaling of NiSi (ST) NiSi on elevated S/D. Applications to FD SOI (LETI, INFINEON) NiSi of strained Si on SiGe( IMEC, PHILIPS)

11 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 11 SUB PROJECT III: New devices § architectures WP III.1.1 Specifications of 45 nm planar devices (ST, PHILIPS, IMEC) WP III.1.2 Integration of modules in bulk CMOS (ST, PHILIPS, IMEC) Gate stack integration: benchmark high k vs oxynitride § poly vs metal gate Shallow junctions integration Strained silicon channel Define best 45 nm compatible planar MOSFET WP III.2.1 Novel devices for the 45 nm node (ST, INFINEON, LETI, CNRS, FhG) Fully depleted thin Si on SOI § SON Multigate devices: planar bonded DG MOS,FINFET, SON WP III.2.2 Novel devices for the 32/22 nm nodes (ST, INFINEON, LETI, CNRS, FhG) Double § triple gate, gate all around using FINFET § SON Co integration with bulk CMOS

12 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 12 SUB PROJECT IV: Multilevel Metallization Modules q WP IV.1 Materials and process (ST/PHILIPS, IMEC, LETI, ZFM) Nanoporous materials: CVD k<2.2, Spin on k<2.0 Barrier materials: ALD WCN < 5 nm, self aligned barriers by electroless q WP IV.2 Dual Damascene architectures (PHILIPS, INFINEON, IMEC, LETI, ZFM, CNRS) Advance patterning 80/80 nm, etching chemistries Start air gap studies for the 32/22 nm nodes q WP IV.3 Modules integration (ST/PHILIPS, ST-I, IMEC, LETI, ZFM, ISILTEC ) Pore sealing: plasma treatments, liner deposition Cu filling: seed repair for conformal PVD layer: CMP: nearly damage free polish with spec uniformity, minimizing dishing, erosion,.. Contact filling: high aspect ratio contacts, minimum barrier thickness by ALCVD dep. q WP IV.4 Reliability (ST/PHILIPS, PHILIPS, IMEC, LETI, ZFM) Thermal properties High frequency characterization Electro migration Cu § Time dependent breakdown of dielectrics and barriers q WP IV.5 Extendibility and beyond Cu (ST/PHILIPS, PHILIPS, ST-I) Ultra narrow lines/spaces(<80 nm) § contact/vias(<50 nm) Wireless interconnects: integrated antenna, test structures

13 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 13 SUB PROJECT V: Process Characterization and Simulation q WP V.1. Process Characterization (ST/PHILIPS,PHILIPS,IMEC, LETI, CNRS) Ultra shallow junctions, dielectrics Junctions down to 10 nm: SIMS, TOFSIMS, MEIS, AFM, SCM, SSRM, EHolography Gate Stacks, dielectrics low k materials High k: HRTEM, EELS, EDX KPS Low k; IRSE, XRR, XR Mechanical stress distributions Main approach UV Ramman Spectroscopy q WP V.2 Process simulation (ST, PHILIPS, INFINEON, CNRS, FhG, ZFM) Support to technology development. Implementation of models into available Software tools Front end Process simulation Back end Process simulation

14 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 14 SUB PROJECT VI: Device Characterization and Simulation q WP VI.1 Device simulation (ST, PHILIPS, INFINEON, CNRS) Simulation for conventional architectures Simulation for novel architectures 45, 32 and 22 nm devices. TCAD with Monte Carlo and quantum codes q WP VI.2 Device modeling for circuit simulation (PHILIPS, MAGWEL) Compact CMOS device models: for circuit simulators Interconnect modeling and simulation Signal propagation and interconnect delay simulations based on resolution -quasi static- of Maxwell equation q WP VI.3 Electrical characterization (PHILIPS, LETI, CNRS, FhG, MAGWEL) Physical, electrical and reliability of dielectrics stacks Electronic transport and mobility

15 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 15 SUB PROJECT VII: Equipment Modules q WP VII.1 Specifications and choice of applications (FhG, ST/PHILIPS) Key applications: SiGe substrate, high k, silicides, CMP Localized analysis areas Plasma diagnostics Large energy optical analysis q WP VII.2 Integrated metrology tools (FhG, ST/PHILIPS, IBS, ISILTEC) Selection of sensors for processing tools Integration into standard cluster ports

16 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 16 SUBPROJECT VIII: Device and MLM process integration. Validation test vehicle WP VIII.1 Front end module integration (ST/PHILIPS, INFINEON, IMEC, FhG) FE test mask vehicle:design Simulation: targets HP,GP, LP. Compact models for SPICE Device and SRAM cell Validation test vehicle Back end module integration (ST/PHILIPS, IMEC, FhG) BE test vehicle Simulation BE Validation test vehicle

17 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 17 SP VIII Objectives q1st objective q1st objective : Integration from SP III (FEOL) and SP IV (BEOL) in a unique process q2nd objective q2nd objective : Validation of FEOL (SRAM cells) and BEOL (2 metal levels ) in 45nm technology qGlobal objective qGlobal objective : provide a key-input for a CMOS045 full CMOS pricess integration in a 300 mm industrial facility

18 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 18 Tentative design rules for first test vehicle Design RulesMinimum pitchShrink factor from 65nm rules Line/Space Active (nm) /80 Poly (nm) /90 Contact (nm) /90 Metal1 (nm) /65 Via-x (nm) /85 Metal-x (nm) /75 Poly-Contact distance (nm) N+/P+ distance (nm) transistor SRAM cell (µm2) Max Gate Density (MGate/mm²)

19 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 19 SRAM Bit celll size - NANOCMOS targets SRAM cell size m 2

20 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 20 Design rules and technology validators The design rules enables competitive validators for the 45nm on FE and BE in terms of SRAM bit-cells and 2 level metallization module The design rules have been established by extrapolating historical and recent literature trends. As the target cell sizes require pitches below 160nm – the lower limit of todays 193nm lithography – the fabrication of the SRAM bit-cells will imply in the first phase of the project the use of e-beam lithography on several critical levels. In parallel, 193nm-lithography should improve by the combination with immersion techniques. For the SRAM bit-cell: four different layouts going from a High Density Design with a 0.334µm2 cell size down to a Ultra-High Density Design of 0.248µm2

21 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 21 SP3/SP4 t0t0 t 0 +24t 0 +18t 0 +12t 0 +6 DRM Specs common SP8/SP3/SP4 Specs common SP3/SP4/SP8 Test-mask Benchmark SRAM/MLM SRAM MLM Consolidated device results Research results First test vehicle Integration results SP8 Timing for FEOL/BEOL test vehicle

22 ITRS Meeting. Stresa, Italy. April 19-20, G. Bomchil. ST Microelectronics 22 CONCLUSIONS q NANOCMOS addresses the main R§D challenges to improve performance and increase integration of logic CMOS Integrated Circuits within the time frame required by the ITRS Roadmap to introduce in production the 45 nm node and anticipate the 32 and 22 nm node generations. q First phase of NANOCMOS plans to demonstrate a representative test vehicle of the 45 nm node in 2005 from a first choice of an appropriate integration scheme among many device architectures and materials. q NANOCMOS would be followed by an industrial oriented project aiming Full 45 nm node logic CMOS process integration in 300 mm wafers. q In parallel a second phase of NANOCMOS will propose the demonstration of feasibility of a 32 nm node technology. q NANOCMOS partners will bring their experience to the ITRS working teams, to contribute to the worldwide consensus building process of a Roadmap as a source of guiding for the Semiconductor Industry.


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