Presentation on theme: "November 29, 2001 Santa Clara , CA"— Presentation transcript:
1November 29, 2001 Santa Clara , CA 2001 ITRS Front End ProcessNovember 29, 2001Santa Clara , CA
2FEP Chapter ScopeThe scope of the FEP Chapter of the ITRS is to define comprehensive future requirements and identify potential solutions for the key technology areas in front-end-of-line IC wafer fabrication processing
3FEP Chapter Topics Starting Substrate Materials Surface Preparation Critical Dimension EtchMOSFET Isolation, Gate Stack, Doping, and Contact RequirementsHigh Performance LogicLow Operating Power Logic (new 2001 addition)Low Standby Power Logic (new 2001 addition)DRAM Trench and Stack Capacitor materials and processes
4FEP Chapter Topics Pre-Metal dielectric layers (new) FLASH memory materials and processes (new)FeRAM materials and processes (new)Non-classical double gate CMOS materials and processes (new)
51999 vs 2001 ITRS Technology Nodes 45 nm gate length was forecasted for year 2008 in 1999 ITRS32 nm gate length was forecasted for year 2011 in 1999 ITRSThere has been an unprecedented acceleration in MOSFET gate length scaling! In many instances, FEP processes have not kept pace, resulting in compromised device performance expectations. This is reflected in the 2001 FEP & PIDS requirements and difficult challenges
6FEP Near Term Difficult Challenges For the years up to and including 2007, with DRAM 1/2 Pitch 65nm, and MPU physical gate length 25nm
7Near Term Difficult Challenges 1 New gate stack processes and materials for continued planar MOSFET scalingRemains the number one FEP priority2 Critical Dimension and MOSFET effective channel length (Leff ) Control3 CMOS integration of new memory materials and processes4 Surfaces and Interfaces; structure, composition, and contamination control5 Scaled MOSFET dopant introduction and control
8Challenge #1 New Gate Stack Processes- Issues Extend oxynitride gate dielectric materials to ~0.8-1nm EOT for high-performance MOSFETSIntroduce and integrate high- gate stack dielectric materials for low operating power MOSFETSControl boron penetration from doped polysilicon gate electrodesMinimize depletion of dual-doped polysilicon electrodesPossible introduction of dual metal gate electrodes with appropriate work function (toward end of period)Metrology issues associated with gate stack electrical and materials characterization
9Gate Stack ChallengesDirect tunneling currents limit allowable gate oxide thickness reduction, thereby limiting gate capacitance and gate control over channel chargeElectrical depletion of doped polysilicon results in unwanted parasitic capacitance that limits gate control of channel charge, ultimately requiring metal gatesFor reference, 1997 ITRS High Performance allowable gate leakage was 1 A/cm2“red wall” for high performance results from reliability and thickness control“red wall” for low power results from lower allowed tunneling curents
10Challenge #2 CD & Leff Control:Issues Control of gate etch processes to yield a physical gate length that is smaller than the printed feature size, while maintaining 10% 3- control of the combined lithography and etch processesControl of profile shape, line and space width for isolated, as well as closely-spaced fine line patternsControl of self-aligned doping introduction process and thermal activation budgets to yield ~ 20% 3- Leff controlMaintenance of CD and profile control throughout the transition to new gate stack materials and processesMetrology
11Resist Trim Process Sequence PhotoresistHardmaskGate PolyGate OxideSubstrateExample150nmExample100nmTrimResistOpenHardmaskEtchGate Poly
12Gate Etch Requirements and Challenges The lithographic, resist trim, and gate etch processes are all assumed to be statistically independent and therefore that the variances (2) are additiveThe variances include all random errors, point to point on a wafer, wafer to wafer and lot to lot, but do not include systematic errors
13Challenge #3 CMOS Integration of New Memory Materials: Issues Development & Introduction of very high- DRAM capacitor dielectric layersMigration of DRAM capacitor structures from Silicon-Insulator-Metal to Metal-Insulator-MetalIntegration and scaling of ferroelectric materials for FeRAMScaling of Flash inter-poly and tunnel dielectric layers may require high-Limited temperature stability of high- and ferroelectric materials challenges CMOS integration
14Technology Migration of Stack Capacitor 130nm nm nm nmMIS MIM MIM MIMMetalBarrier MetalPerovskiteepi-BSTBSTTiNTa2O5Poly Si
16Challenge #4 Surfaces & Interfaces: Issues Contamination, composition and structure control of channel/gate dielectric interfaceContamination, composition and structure control of gate dielectric/gate electrode interfaceInterface control of DRAM capacitor structuresMaintenance of surface and interface integrity through full-flow CMOS processStatistically significant characterization of surfaces having extremely low defect concentrationsStarting materialsPre-gate cleans
18Challenge #5 Scaled MOSFET Doping: Issues Doping and activation processes to achieve source/drain parasitic resistance that is less than ~16-20% of ideal channel resistance (=Vdd/Ion)Control of parasitic capacitance to achieve less than ~19-27% of gate capacitance with acceptable Ion and short channel effectAchievement of activated doping concentration greater than solid solubility levels in dual doped polysilicon gate electrodesFormation of continuous self-aligned silicon contacts over shallow source/drain regionsMetrology issues associated with 2-D doping profiling
19Scaled MOSFET Parasitic Resistance Elements Accumulation and Spreading resistancesExtension Sheet ResistivityContact Junction Sheet ResistivityContact Resistivity
20Ideal MOSFET Contact Scaling Halo Implant manages SCE from deeper contactSilicide contact 1/2 of contact region depth1/2 x in 4 yearsDrain Extension Depth Scales with Gate LengthSilicon/Silicide interfacial resistivity is crucial to low contact area resistanceContact Region Depth Scales more slowly than Gate Length, depending on efficacy of halo
21PIDS Forecasted High Performance MOSFET Parasitic Elements
22MOSFET Contact Requirements The concomitant achievement of drain extension junction depth and sheet resistance poses a major doping challengeContact silicide thickness must scale with contact junction depth, making the achievement of a continuous, thin silicide film increasingly difficult to achieveThe contact area is assumed to scale with the ASIC half pitch, resulting in a progressively smaller source/drain contact area. As a consequence the maximum allowable silicide/silicon contact resistivity must be progressively lowered.
23FEP Long Term Difficult Challenges For the years beyond 2007, with DRAM 1/2 Pitch < 65nm, and MPU physical gate length <25nm
24Long Term FEP Challenges Continued scaling of planar CMOS devicesIntroduction and CMOS integration of non-standard double-gate MOSFET devicesThese devices may be needed as early as 2007Increased allocation of long term research resources would be highly desireableStarting material alternatives beyond 300mmNew memory storage cells, storage devices and memory architecturesSurfaces and Interfaces; structure, composition, and contamination control
25Challenge #3 Starting Material Alternatives Beyond 300mm: Issues Future productivity enhancement needs dictate the requirement for a next generation, large substrate materialHistorical trends suggest that the new starting material have nominally 2X present generation area, e.g. 450mmCost-effective scaling of the incumbent Czochralzki crystal pulling and wafer slicing process is questionableResearch is required for a cost-effective substrate alternative
26FeRAM Roadmap S. Kawamura (FEP) Here’s a newcomer… November 2001 FEP & PIDS ITWGFeRAM RoadmapHere’s a newcomer…S. Kawamura (FEP)
27Why FeRAM? FeRAM has the following outstanding features: *Non-volatility*Low voltage (power) operation*High speed*High endurance*High integration (Cell structure is similar to DRAM.)
32FeRAM vs. DRAMGiga scale integration will be available with a 3D capacitor(bit)Capacity (Mb)PlateFerro. FilmStorage Node3D1T1CYear
33Qsw and Capacitor Structure Qsw/2Pr=Required Capacitor Area> Projected Capacitor Size3D.N.B. Conventional structures can be used for 0.18um if we have Ferroelectric materials with 2Pr=34.5uC/cm2.
34Issues (1) In order to enjoy (Lambs) “The Silence of the (other) RAM’s,”reliability comes first to be focused on,followed by application and cost.
35Issues (2) Ferroelectric materials: Should be stable under thermal budgets.Usually being used with some dopants.*) SBT at present gives less than adequate switching charge for 2005 and beyond.#) Chemical Solution DepositionPZT:Pb(Zr,Ti)O3, SBT:SrBi2Ta2O9, BLT:(Bi,La)4Ti3O12
36Issues (3)Fatigue:More than 1E+15 is required to compete with SRAM and DRAM. Practical testing is critical.
37Issues (4) Application: Cost: Limited to small capacity (embedded) memory for RFID, Smart Card, etc.Some “killer applications” should be needed to establish FeRAM market.Cost:Not competitive due to large cell size. 1T1C and 3D capacitor are mandatory to reduce cost.