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24 July 2002 Work In Progress – Not for Publication The International Technology Roadmap for Semiconductors Overall Roadmap Technology Characteristics.

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Presentation on theme: "24 July 2002 Work In Progress – Not for Publication The International Technology Roadmap for Semiconductors Overall Roadmap Technology Characteristics."— Presentation transcript:

1 24 July 2002 Work In Progress – Not for Publication The International Technology Roadmap for Semiconductors Overall Roadmap Technology Characteristics (ORTC) Overview 07/24/02 Alan Allan / Intel Corporation

2 24 July 2002 Work In Progress – Not for Publication Key Messages NO CHANGES to the 2002 ORTC Scaling targets and Chip Size models – First Time Since 1994 NTRS! Economics (Chip Size) OK through 2004 Performance (Frequency) OK through 2004 Density (Functionality) OK through 2004 But Remember: 1995-2001 2-year Scaling Node Rate… …And Trends Slip from Historical Rates after 2005 Room for Improvement in 2003: –Clarification of Node and Production Definitions; –Watch for Evidence of Industry Acceleration in 2003

3 24 July 2002 Work In Progress – Not for Publication Production Definition

4 24 July 2002 Work In Progress – Not for Publication Production Ramp-up Model and Technology Node Volume (Parts/Month) 1K 10K 100K Months 0 -24 1M 10M 100M Alpha Tool 1224 -12 DevelopmentProduction Beta Tool Production Tool First Conf. Papers First Two Companie s Reaching Production Volume (Wafers/Month) 2 20 200 2K 20K 200K Source: 2001 ITRS - Exec. Summary

5 24 July 2002 Work In Progress – Not for Publication Technology Node vs Actual Wafer Production Capacity 0.01 0.1 1 10 1995 2000 2005 Year 19961997199820011999200420032002 W.P.C. Feature Size (Half Pitch) ( m) 0.01 0.1 1 10 1995 2000 2005 Year 19961997199820011999200420032002 W.P.C. ITRS Technology Node W.P.C.= Total Worldwide Wafer Production Capacity (Relative Value) Sources: 1995 to 1999: SICAS 2000: Yano Research Institute& SIRIJ Feature Size of Technology >0.7 m 0.4-0.7 m <0.4 m >0.8 m 0.5-0.8 m 0.35-0.5 m 0.25- 0.35 m 0.2 - 0.25 m 0.18 - 0.2 m <0.18 m For 1995-1999 For 2000 Source: 2001 ITRS - Exec. Summary

6 24 July 2002 Work In Progress – Not for Publication Scaling – Technology Nodes

7 24 July 2002 Work In Progress – Not for Publication MOS Transistor Scaling (1974 to present) S=0.7 [0.5x per 2 nodes] Pitch Gate

8 24 July 2002 Work In Progress – Not for Publication Half Pitch (= Pitch/2) Definition (Typical MPU/ASIC) (Typical DRAM) Poly Pitch Metal Pitch Source: 2001 ITRS - Exec. Summary

9 24 July 2002 Work In Progress – Not for Publication 2001 ITRS – (No Changes for 2002 Update) SCALING Timing Highlights Technology Node and Industry Pace: The DRAM Half-Pitch (HP) on a 3-year-cycle trend after 130nm/2001 The MPU/ASIC HP remains on a 2-year-cycle trend until 90nm/2004, and then remains equal to DRAM HP (3-year cycle) The MPU Printed Gate Length (Pr GL ) and Physical Gate Length (Ph GL) will be on a 2-year-cycle until 45nm and 32nm, respectively, until the year 2005 The MPU Pr GL and Ph GL will proceed parallel to the DRAM/MPU HP trends on a 3-year cycle beyond the year 2005 The ASIC/Low Power Pr/Ph GL is delayed 2 years behind MPU Pr/Ph GL ASIC HP equal to MPU HP

10 24 July 2002 Work In Progress – Not for Publication 2001 ITRS ORTC Node Tables – w/Node Cycles [3-Year Node Cycle] [2-year cycle][3-year cycle] [Node = DRAM Half-Pitch (HP)] [MPU Gate Length Cycle (GL)]: [MPU HP/GL Cycle]:

11 24 July 2002 Work In Progress – Not for Publication Source: 2001 ITRS - Exec. Summary, ORTC

12 24 July 2002 Work In Progress – Not for Publication Source: 2001 ITRS - Exec. Summary, ORTC

13 24 July 2002 Work In Progress – Not for Publication 2001 ITRS ORTC MPU Frequency Tables – w/Node Cycles Table 4c Performance and Package Chips: Frequency On-Chip Wiring LevelsNear-Term Years Y EAR OF P RODUCTION 2001 2002 2003 2004 2005 2006 2007 DRAM ½ Pitch (nm) 130 115 100 90 80 70 65 MPU/ASIC ½ Pitch (nm) 150 130 107 90 80 70 65 MPU Printed Gate Length (nm) 90 75 65 53 45 40 35 MPU Physical Gate Length (nm) 65 53 45 37 32 28 25 Chip Frequency (MHz) On - chip local clock 1,684 2,317 3,088 3,990 5,173 5,631 6,739 Chip-to-board (off-chip) speed (high-performance, for peripheral buses)[1] 1,684 2,317 3,088 3,990 5,173 5,631 6,739 Maximum number wiring levelsmaximum 7 8 8 8 9 9 9 Maximum number wiring levelsminimum 7 7 8 8 8 9 9 Table 4d Performance and Package Chips: Frequency, On-Chip Wiring LevelsLong-term Years Y EAR OF P RODUCTION 2010 2013 2016 DRAM ½ Pitch (nm) 45 32 22 MPU/ASIC ½ Pitch (nm) 45 32 22 MPU Printed Gate Length (nm) 25 18 13 MPU Physical Gate Length (nm) 18 13 9 Chip Frequency (MHz) On - chip local clock 11,511 19,348 28,751 Chip-to-board (off-chip) speed (high-performance, for peripheral buses)[1] 11,511 19,348 28,751 Maximum number wiring levelsmaximum 10 Maximum number wiring levelsminimum 9 9 10 [2-Yr GL Cycle; then 3-Yr] [3-year cycle] Sources: 2001 ITRS ORTC [MPU Gate Length Cycle (GL)]:

14 24 July 2002 Work In Progress – Not for Publication

15 DRAM Cell Area History / 2001 ITRS Model DRAM Cell Area 0.001 0.01 0.1 1 10 19861989199219951998200120042007201020132016 Year Cell Area (u2) History <--2000 --> F'cast 1Gb / 2Gb CAF (A) = 6 4Gb / 8Gb CAF (A) = 6 16Gb / 32Gb CAF (A) = 4 64 Gb/128Gb CAF (A) = 4 64 Mb CAF (A) = 11 = 1.3/.35^2;.71/.25^2 16->10 (per FEP) 4 Mb CAF (A) = 22 = 11/.71^2 26 (per FEP) 16 Mb CAF (A) = 16 = 4.0/.5^2 21 (per FEP) 1 Mb (est.) CAF (A) = 31 = 31/1.0^2 29 (per FEP) 128/256Mb CAF (A) = 8.0 =.35/.21^2;.26/.18^2 10 -> 8 (per FEP) Actual Scaling Acceleration, Or Equivalent Scaling Innovation Needed to maintain historical trend DRAM Cell Size Historical Trend: Half-Pitch Scaling, contributed ~.5x / 3 years [(.7x)^2] Cell Design innovation contributed additional ~.7x / 3 years 0.35x / 3 Years –29%/yr Historical Actual 2001 ITRS Sources: Sematech, 2001 ITRS ORTC 512Mb

16 24 July 2002 Work In Progress – Not for Publication Chip Size Trends

17 24 July 2002 Work In Progress – Not for Publication Chip Size Model Calculation Illustration - DRAM (Cell Array Area / Chip Size) x 100 = Cell Array Efficiency (%): Chip Size = (A x f 2 x Nbits)/CAE f 2 Cell Area = Cell Area Factor (A) x f 2 ; f = technology node (half-pitch) feature size; Example: Cell Area = 2x4 x f 2 = 8 f 2 Cell Array Area = Cell Area x number of bits (2 n )

18 24 July 2002 Work In Progress – Not for Publication 572mm2 Litho Field Size 286mm2 2 per Field Size 800mm2 Litho Field Size MPU Chip size (mm2) – Historical Trends vs 2001 ITRS Model* 1000 100 10 198019851990199520002005201020152020 CP MPU 140mm2 HP MPU 310mm2 CP Shrink 70mm2 * ITRS Design TWG MPU Transistors/Chip Model: ~2x/Node = 2x/2yrs from 1999 - 2001; then 2x/3yrs from 2001- 2016 *1999 Leading- Edge.18u CP MPU: 512KB (28Mt [58.3%] x 1.18u2/t = 34mm2) + 20Mt Logic x 5.19u2/t = 104mm2 + 2mm2 OH= 106mm2 = Total 48Mt x ave 2.92u2/t = 140mm2 *1999 Leading- Edge.18u HP MPU: 2MB (113Mt [81.9%] x 1.18u2/t = 135mm2) + 25Mt Logic x 5.19u2/t = 130mm2 + 45mm2 OH= 310mm2 = Total 138Mt x ave 2.25u2/t = 310mm2

19 24 July 2002 Work In Progress – Not for Publication Density Trends (bits/cm2, t/cm2) – ITRS / ORTC ITRS 2001 Moores Law Targets: DRAM: 2x/2.5yrs; 1.05x/yr Chip Size MPU: 2x/node = 2x/3years; FLAT Chip Size

20 24 July 2002 Work In Progress – Not for Publication Key Messages NO CHANGES to the 2002 ORTC Scaling targets and Chip Size models Economics (Chip Size) OK through 2004 Performance (Frequency) OK through 2004 Density (Functionality) OK through 2004 But Remember: 1995-2001 2-year Scaling Node Rate… …And Trends Slip from Historical Rates after 2005 Room for Improvement in 2003: –Clarification of Node and Production Definitions; –Watch for Evidence of Industry Acceleration in 2003

21 24 July 2002 Work In Progress – Not for Publication 3-yr Node Cycle vs 2-yr 0.89/yr 0.95/yr 0.71/yr 0.74/yr [Cell Design Improvement Factor] 2001 ITRS DRAM Model Trend Analysis

22 24 July 2002 Work In Progress – Not for Publication 1.59/yr 1.41/yr 0.71/yr 0.74/yr 1.26/yr 1.47/yr 1.34/yr 2001 ITRS DRAM Model Trend Analysis (cont.)

23 24 July 2002 Work In Progress – Not for Publication 250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16 0.5x 0.7x NN+1N+2 Node Cycle Time (T yrs): *CARR(T) = [(0.5)^(1/2T yrs)] - 1 CARR(3 yrs) = -10.9% CARR(2 yrs) = -15.9% * CARR(T) = Compound Annual Reduction Rate (@ cycle time period, T) Log Half-Pitch Linear Time 1994 NTRS -.7x/3yrs Actual -.7x/2yrs Source: 2001 ITRS - Exec. Summary Scaling Calculator + Node Cycle Time:


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