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18 July 2001 Work In Progress – Not for Publication 2001 ITRS Front End Process July 18, 2001 San Francisco, CA.

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Presentation on theme: "18 July 2001 Work In Progress – Not for Publication 2001 ITRS Front End Process July 18, 2001 San Francisco, CA."— Presentation transcript:

1 18 July 2001 Work In Progress – Not for Publication 2001 ITRS Front End Process July 18, 2001 San Francisco, CA

2 18 July 2001 Work In Progress – Not for Publication FEP Chapter Scope The scope of the FEP Chapter of the ITRS is to define comprehensive future requirements and identify potential solutions for the key technology areas in front-end-of-line IC wafer fabrication processing

3 18 July 2001 Work In Progress – Not for Publication FEP Chapter Topics Starting Substrate Materials Surface Preparation Critical Dimension Etch MOSFET Isolation, Gate Stack, Doping, and Contact Requirements –High Performance Logic –Low Operating Power Logic (new 2001 addition) –Low Standby Power Logic (new 2001 addition) DRAM Trench and Stack Capacitor materials and processes

4 18 July 2001 Work In Progress – Not for Publication Pre-Metal dielectric layers (new) FLASH memory materials and processes (new) FeRAM materials and processes (new) Non-classical double gate CMOS materials and processes (new) FEP Chapter Topics

5 18 July 2001 Work In Progress – Not for Publication 1999 vs 2001 ITRS Technology Nodes 45 nm gate length was forecasted for year 2008 in 1999 ITRS 32 nm gate length was forecasted for year 2011 in 1999 ITRS There has been an unprecedented acceleration in MOSFET gate length scaling! In many instances, FEP processes have not kept pace, resulting in compromised device performance expectations. This is reflected in the 2001 FEP & PIDS requirements and difficult challenges

6 18 July 2001 Work In Progress – Not for Publication FEP Near Term Difficult Challenges For the years up to and including 2007, with DRAM 1/2 Pitch 65nm, and MPU physical gate length 25nm

7 18 July 2001 Work In Progress – Not for Publication Near Term Difficult Challenges 1 New gate stack processes and materials for continued planar MOSFET scaling Remains the number one FEP priority 2 Critical Dimension and MOSFET effective channel length (L eff ) Control 3 CMOS integration of new memory materials and processes 4 Surfaces and Interfaces; structure, composition, and contamination control 5 Scaled MOSFET dopant introduction and control

8 18 July 2001 Work In Progress – Not for Publication Challenge #1 New Gate Stack Processes- Issues Extend oxynitride gate dielectric materials to ~0.8-1nm EOT for high-performance MOSFETS Introduce and integrate high- gate stack dielectric materials for low operating power MOSFETS Control boron penetration from doped polysilicon gate electrodes Minimize depletion of dual-doped polysilicon electrodes Possible introduction of dual metal gate electrodes with appropriate work function (toward end of period) Metrology issues associated with gate stack electrical and materials characterization

9 18 July 2001 Work In Progress – Not for Publication Gate Stack Challenges Direct tunneling currents limit allowable gate oxide thickness reduction, thereby limiting gate capacitance and gate control over channel charge Electrical depletion of doped polysilicon results in unwanted parasitic capacitance that limits gate control of channel charge Earlier red wall for low power results from lower allowed tunneling curents

10 18 July 2001 Work In Progress – Not for Publication Challenge #2 CD & L eff Control:Issues Control of gate etch processes to yield a physical gate length that is smaller than the printed feature size, while maintaining 15% 3- control of the combined lithography and etch processes Control of profile shape, line and space width for isolated, as well as closely-spaced fine line patterns Control of self-aligned doping introduction process and thermal activation budgets to yield ~ 25% 3- L eff control Maintenance of CD and profile control throughout the transition to new gate stack materials and processes Metrology

11 18 July 2001 Work In Progress – Not for Publication Resist Trim Process Sequence Photoresist Hardmask Gate Poly Gate Oxide Substrate Example 150nm Example 100nm Trim Resist Open Hardmask Etch Gate Poly

12 18 July 2001 Work In Progress – Not for Publication Challenge #3 CMOS Integration of New Memory Materials: Issues Development & Introduction of very high- DRAM capacitor dielectric layers Migration of DRAM capacitor structures from Silicon- Insulator-Metal to Metal-Insulator-Metal Integration and scaling of ferroelectric materials for FeRAM Scaling of Flash inter-poly and tunnel dielectric layers may require high- Limited temperature stability of high- and ferroelectric materials challenges CMOS integration

13 18 July 2001 Work In Progress – Not for Publication Technology Migration of Stack Capacitor 130nm 100nm 80nm 65nm MIS MIM MIM MIM TiN Ta2O5 Poly Si Metal Barrier Metal BST Perovskite epi-BST

14 18 July 2001 Work In Progress – Not for Publication Selection from DRAM Stack Capacitor Roadmap

15 18 July 2001 Work In Progress – Not for Publication FLASH Memory SourceDrain Floating Gate Control Gate Tunnel Oxide Interpoly Oxide Operating Principle: Charge stored on the floating gate (a bit), will determine whether a voltage applied to the control gate turns the MOSFET on or off. (read)

16 18 July 2001 Work In Progress – Not for Publication FLASH Roadmap Issues: Scaling of the NOR L gate Tunnel oxide must be thick enough to assure charge retention, but thin enough to allow lower write voltage Interpoly oxide must be thick enough to assure charge retention bu thin enough assure almost constant coupling ratio, making charge retention difficult.

17 18 July 2001 Work In Progress – Not for Publication Challenge #4 Surfaces & Interfaces: Issues Contamination, composition and structure control of channel/gate dielectric interface Contamination, composition and structure control of gate dielectric/gate electrode interface Interface control of DRAM capacitor structures Maintenance of surface and interface integrity through full-flow CMOS process Statistically significant characterization of surfaces having extremely low defect concentrations –Starting materials –Pre-gate cleans

18 18 July 2001 Work In Progress – Not for Publication Pre-Gate Clean Requirements

19 18 July 2001 Work In Progress – Not for Publication Challenge #5 Scaled MOSFET Doping: Issues Doping and activation processes to achieve source/drain parasitic resistance that is less than ~16-20% of ideal channel resistance (=V dd /I on ) Control of parasitic capacitance to achieve less than ~19-27% of gate capacitance with acceptable I on and short channel effect Achievement of activated doping concentration greater than solid solubility levels in dual doped polysilicon gate electrodes Formation of continuous self-aligned silicon contacts over shallow source/drain regions Metrology issues associated with 2-D doping profiling

20 18 July 2001 Work In Progress – Not for Publication Scaled MOSFET Parasitic Resistance Elements Spreading and Accumulation resistances Extension Sheet Resistivity Contact Junction Sheet Resistivity Contact Resistivity

21 18 July 2001 Work In Progress – Not for Publication Parasitic Capacitance Elements Gate/Drain Overlap Capacitance Halo/Extension Junction Capacitance Contact Junction Capacitance

22 18 July 2001 Work In Progress – Not for Publication PIDS Forecasted High Performance MOSFET Parasitic Elements

23 18 July 2001 Work In Progress – Not for Publication FEP Long Term Difficult Challenges For the years beyond 2007, with DRAM 1/2 Pitch < 65nm, and MPU physical gate length <25nm

24 18 July 2001 Work In Progress – Not for Publication Long Term FEP Challenges 1Continued scaling of planar CMOS devices 2Introduction and CMOS integration of non- standard double-gate MOSFET devices These devices may be needed as early as 2007 Increased allocation of long term research resources would be highly desireable 3Starting material alternatives beyond 300mm 4New memory storage cells, storage devices and memory architectures 5Surfaces and Interfaces; structure, composition, and contamination control

25 18 July 2001 Work In Progress – Not for Publication Challenge #1- Continued Planar MOSFET Scaling; Issues Higher- gate dielectric materials Dual metal gate electrodes with appropriate work function Possible single drain MOSFETs with elevated contacts CMOS Integration consistent with higher- temperature constraints CD and L eff control Chemical, electrical, and structural characterization

26 18 July 2001 Work In Progress – Not for Publication Challenge #2 Dual-Gate MOSFETS: Issues Selection and characterization of optimum device types Device performance and reliability characterization CMOS Integration with other devices, including planar MOSFETS Introduction, characterization, and production hardening of new FEP unit processes Metrology

27 18 July 2001 Work In Progress – Not for Publication Challenge #3 Starting Material Alternatives Beyond 300mm: Issues Future productivity enhancement needs dictate the requirement for a next generation, large substrate material Historical trends suggest that the new starting material have nominally 2X present generation area, e.g. 450mm Cost-effective scaling of the incumbent Czochralzki crystal pulling and wafer slicing process is questionable Research is required for a cost-effective substrate alternative

28 18 July 2001 Work In Progress – Not for Publication Challenge #4 New Memory Devices; Issues Scaling DRAM storage cells beyond 6F 2 and ultimately to 4F 2 Possible further scaling of Flash memory interpoly- and tunnel-oxide thickness FeRAM storage cell scaling Introduction of new memory types and storage concepts

29 18 July 2001 Work In Progress – Not for Publication Challenge #5 Surface & Interface Control; Issues Achievement and maintenance of structural, chemical, and contamination control over surfaces and interfaces that may be horizontally or vertically oriented relative to the chip surface Statistically significant characterization of surfaces and interfaces having extremely low defect counts Metrology and characterization of surfaces and interfaces that may be horizontally or vertically oriented relative to the chip surface.

30 18 July 2001 Work In Progress – Not for Publication FeRAM Roadmap Heres a newcomer… July 2001 FEP & PIDS ITWG S. Kawamura (FEP)

31 18 July 2001 Work In Progress – Not for Publication Why FeRAM? FeRAM has the following outstanding features: –Non-volatility –Low voltage (power) operation –High speed –High Endurance –Capable of high levels of integration cell size similar to DRAM

32 18 July 2001 Work In Progress – Not for Publication FeRAM Roadmap (version 7.0)

33 18 July 2001 Work In Progress – Not for Publication Assumptions (1) Feature Size: 0.35 m expected to be available in early 2002, 0.25 m in x0.7 every 1-3 years. Memory Capacity: Intend to be aggressive to establish FeRAM market. x4 every 1-3 years.

34 18 July 2001 Work In Progress – Not for Publication Assumptions (2) Cell Size: planar stack (x 0.6) 2T2C 1T1C (x 0.6) Switching Charge Qsw: Constant V bitline =140mV for sensing Qsw=C bitline x V bitline (Stack) Plate Ferro. Film Storage Node (Planar) Storage Node Ferro. Film Plate

35 18 July 2001 Work In Progress – Not for Publication Evolution in Cell Structure Planar Cell Stack Cell (COB) Stack Cell (CUB) 3D Capacitor Bit Line Word Line Capacitor W, etc. Ferroelectic Film Pt, IrO 2, etc. Metal Bit Line (Polycide, W, etc.) Bit Line (Polycide, W, etc.) Al (Polycide, W, etc.)

36 18 July 2001 Work In Progress – Not for Publication FeRAM vs. DRAM Year Capacity (Mb) Giga scale integration will be available with a 3D capacitor Plate Ferro. Film Storage Node 1T1C 3D

37 18 July 2001 Work In Progress – Not for Publication V bitline Estimation Based on DRAM roadmap, V bitline estimated to be 140mV.

38 18 July 2001 Work In Progress – Not for Publication Qsw and Capacitor Structure Qsw/2Pr=Required Capacitor Area> Projected Capacitor Size 3D.

39 18 July 2001 Work In Progress – Not for Publication In order to enjoy (Lambs) The Silence of the (other) RAMs, reliability comes first to be focused on, followed by application and cost. Issues (1)

40 18 July 2001 Work In Progress – Not for Publication Issues (2) *) Since the PZT contains the lead, it may pose a problem from the viewpoint of ESH. #) Chemical Solution Deposition Ferroelectric materials: Should be stable under thermal budgets. Usually being used with some dopants. PZT:Pb(Zr,Ti)O3, SBT:SrBi2Ta2O9, BLT:(Bi,La)4Ti3O12

41 18 July 2001 Work In Progress – Not for Publication Fatigue: More than 1E+15 cycles are required to compete with SRAM and DRAM. Practical testing is critical. Issues (3)

42 18 July 2001 Work In Progress – Not for Publication Application: Limited to small capacity (embedded) memory for RFID, Smart Card, etc. Some killer applications should be needed to establish FeRAM market. Cost: Not competitive due to large cell size. 1T1C and 3D capacitor are mandatory to reduce cost. Issues (4)


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