1. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation TWG Attendees Wim ShoenmakerEurope Gilles Le CarvalEurope Herve JaouenEurope Jurgen LorenzEurope Wolfgang MolzerEurope Norihiko KotaniJapan Ed HallUS

2. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Meeting Accomplishments Reviewed difficult challenges Reviewed tables drafted by Japan team. Assigned responsibilities for difficult challenges, tables, and text. Met with 6 TWGs ( Design, FEP, Interconnect, Assembly and Packaging, Process Integration, and Litho) – brainstormed critical modeling needs.

3. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation TWG Responsibilities Difficult Challenges – Europe Tables – Japan Text coordination - US

4. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Sub chapter section responsibilities Equipment / Feature ScaleUS - Hall LithoUS – Hall Front endEurope – Lorenz Numerical deviceEurope – Shoenmaker Circuit elementsUS – Richardson PackageUS – open Numerical methodsEurope - Lorenz Materials ModelingUS – Hall Backend (interconnect)Europe – Sh\choenmaker Integration US - Hall

5. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation sub-Chapters Start from previous text Integrate cross-TWG needs Work with Japan to sharpen words for tables Get input from others Drafts due mid-June

6. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Difficult Challenges – draft To 65nm – through 2007 –High frequency modeling Need frequency goals,relation to design, packaging and materials –Modeling of ultra-shallow junctions Silicidation, new dopants, plasma doping –Back end process modeling Add CMP, wafer/feature, larger diameter wafers –Lithography Optical print limits, resist modeling, NGL –Gate Stack Materials to transport prediction

7. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Difficult Challenges Sub 65nm –Continuum to atomistic transition – modeling tools –Ultimate CMOS simulation capability –Emerging devices –Mechanical modeling Stress voiding, electromigration, piezoelectric effects, fracture, adhesion, stress induced diffusion

8. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Difficult Challenges Notes – action items –Remove package modeling from critical list? –Moved gate stack to shorter difficult challenge –Include interconnect modeling? Include reliability modeling –Final form due June 15 to SEMATECH

9. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Tables 87a,b,c Japan group to coordinate and drive –Need information on cost model –Need to fix colors –Table 87c- need to remove first column

10. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Cross-TWG Brainstorming - Packaging Co-design integration software tools –Thermal, mechanical, electrical –Chip and package –RF capability –Parameter passing EMI Numerical methods Fracture / fatique Transient temperature simulations Optical / electrical

11. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Cross-TWG Brainstorming – Lithography – with priorities and timing EUV – reflective, defect tolerant issues ( high; long term) EPL – electron projection litho resolution vs thruput (H, medium timing) High numerical aperture (H, short term need). Lens roughness (Medium priority, long term). Phase shift ( medium priority, short term need). Defect tolerant optical simulation (short term need – there exist tools today). EUV overlay ( need input parameters; high priority, short or long term need).

12. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Cross-TWG Brainstorming – Lithography – with priorities and timing – con't Chemically amplified resists; post exposure bake. ( high priority – short / long term need) Thin resists; dual resists – link of litho to etch – 3 sigma predictions ( short/ long term need)

13. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Cross-TWG Brainstorming – Interconnect – with priorities and timing (Harold Hosack – contact person) Cross talk - materials issues, variability, RLC, passives ( high priority, short term need) Thermal modeling – multi-layer metallizations; mechanical, stresses, thermal cycling (high priority, short term need). Electromigration, stress voiding, (medium priority). Planarization – shear stress issues for low-k, dummy features, models to determine if interconnect specs can be met ( high priority). Deposition/ etch – (low priority)

14. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Cross-TWG Brainstorming – Interconnect – with priorities and timing – con't Low k models – chemistry (medium priority) Optical interconnects ( medium priority).

15. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Cross-TWG Brainstorming – Design ( Andrew Kahng – contact person) Interconnect variations Device variability Functional defect screening Best practice analysis for design Frequency roadmap Ioff/Ion tools Validation and test structures Substrate noise I.e model to optimize design

16. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Cross-TWG Brainstorming – Process Integration – with priorities and timing RF – mixed signal (medium priority, short term) Gate stack ( high priority, short term needs) –Materials to electrical properties. –Structure stability 3D Process and Device simulators (high priority, short term need) –Improve usability, accuracy, capabilities Quantum effects ( high priority, short term need). Heterostructures ( medium priority, medium time frame).

17. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Cross-TWG Brainstorming – Process Integration – with priorities and timing – con't Heterostructures 9 medium priority, short term needs ). Non-bulk CMOS ( high priority, short term need). MRAM ( low priority, medium time frame). Emerging devices ( lower priority)

18. April 26-27, 2001 Ed Hall Work in Progress – Not for Publication Modeling and Simulation Cross-TWG Brainstorming – Front End Processing– with priorities and timing SiGeC – channel, source/drain, high doping issues (medium priority, short term needs). Metastable activation – poly gate, source/drain (medium proirity, medium or short time). 450 mm Czochralski growth modeling – feasibility Plasma immersion doping (low priority). ALD ( high priority, short term needs ). Gate stack -including interface charge, impurity diffusion, barrier heights,( high priority, short/long term needs). Spike annealing ( high priority, short term need).