5FeRAM vs. DRAMGiga scale integration will be available with a 3D capacitor.Capacity (Mb)PlateFerro. FilmStorage Node3D1T1CYear
6DVbitline EstimationBased on DRAM roadmap, DVbitline estimated to be 140mV.
7Qsw and Capacitor Structure Qsw/2Pr=Required Capacitor Area> Projected Capacitor Size3D.
8Issues 1 In order to enjoy “The Silence of the (other) RAM’s,” Reliability comes first to be focused on.*Ferroelectric materials: Should be stable under thermal budgets.*Fatigue: Some 1E+15 is required to compete with SRAM and DRAM.
9Issues 2 Application: Cost: Limited to small capacity embedded memory. Some “killer applications” should appear to establish FeRAM market.Cost:Not competitive due to large cell size. 1T1C and 3D capacitor are mandatory to reduce cost.
10Acknowledgements FEP & PIDS WG (Japan) would like to thank many researchers in this field inJapan:for the basic information and comments to draw up the roadmap, andthe United States and Europe:for their useful comments to it .