1. Work in Progress --- Not for Publication 6 December 2000 1 Interconnect Working Group ITRS 2000 Lakeshore Hotel, Hsinchu, Taiwan, R.O.C. 6 December 2000 Christopher Case Douglas Yu

2. Work in Progress --- Not for Publication 6 December 2000 2 ITWG Regional Contributors Japan Shinichi Ogawa Riichirou Aoki Yuji Furumura Taiwan Chen-Hua Douglas Yu Calvin Hsueh US Robert Geffken Christopher Case Europe Hans Joachim-Barth Gerhard Goltz Korea Hyeon-Deok Lee Hyunchul Sohn

3. Work in Progress --- Not for Publication 6 December 2000 3 Agenda Review of 1999 difficult challenges Key issues –Technology Requirements –Potential Solutions Updated tables 2001 preview Summary

4. Work in Progress --- Not for Publication 6 December 2000 4 Typical Chip Cross-section of Hierarchical Scaling Wire Via Global Intermediate Local Passivation Dielectric Etch Stop Layer Dielectric Diffusion Barrier Copper Conductor with Metal Barrier Liner Pre Metal Dielectric Tungsten Contact Plug

5. Work in Progress --- Not for Publication 6 December 2000 5 Difficult Challenges New materials Reliability Process integration Dimensional control Interconnect process with low/no device impact New materials and size effects Process integration Dimensional control Aspect ratios for fill and etch Solutions beyond copper and low <100 nm> 100 nm

6. Work in Progress --- Not for Publication 6 December 2000 6 Technology Requirement Issues Reliability requirements Usage of Optional Levels Planarization requirements Dielectric metrics including effective Is aggressive barrier thickness requirement (i.e. 0) needed for global wiring level - all 3 tables

7. Work in Progress --- Not for Publication 6 December 2000 7 MPU Near Term Years Constant reliability still requires improvement in defect density - based on 5 FITS and high performance MPU

8. Work in Progress --- Not for Publication 6 December 2000 8 MPU Near Term Years No significant dishing at local levels - thinning due to erosion over large areas (50% areal coverage)

9. Work in Progress --- Not for Publication 6 December 2000 9 MPU Near Term Years New combined dishing/erosion metric for global wire Cu thinning due to dishing for isolated lines/pads

10. Work in Progress --- Not for Publication 6 December 2000 10 MPU Near Term Years Expanded range of dielectric constants Return of bulk dielectric constant target specification

11. Work in Progress --- Not for Publication 6 December 2000 11 MPU Long Term Years Conductor effective resistivity relaxed along with barrier targets Similar changes proposed to SoC table

12. Work in Progress --- Not for Publication 6 December 2000 12 Typical Chip Cross-section of Hierarchical Scaling Wire Via Global Intermediate Local Passivation Dielectric Etch Stop Layer Dielectric Diffusion Barrier Copper Conductor with Metal Barrier Liner Pre Metal Dielectric Tungsten Contact Plug

13. Work in Progress --- Not for Publication 6 December 2000 13 Challenges High and ferroelectrics materials development Development and integration of ultra low materials with acceptable mechanical/thermal properties Fabricating low-temp low-loss SiO 2 optical interconnect Addressing turning radius of higher loss polymer optics Dielectric Potential Solutions Minor Corrections High and terminology for porous

14. Work in Progress --- Not for Publication 6 December 2000 14 Challenges Solutions for high A/R DRAM contacts Conformal barriers for dual damascene Cu - thin, effective diffusion barrier for low via resistance Barrier Potential Solutions Correction Addition of Atomic Layer Deposition

15. Work in Progress --- Not for Publication 6 December 2000 15 Barriers compatible with cooled conductors Challenges High A/R Al vias Nucleation layers other than TiN for high A/R DRAM contacts Advanced nucleation layers for Cu interconnect which do not degrade conductor effective resistivity Nucleation Potential Solutions Addition ECD Cu seed repair

16. Work in Progress --- Not for Publication 6 December 2000 16 Challenges Low temp CVD W for low compatibility High A/R contact fill for DRAM Cu fill of dual damascene structures with reduced CD and high A/R Identifying and implementing solutions after Cu and low Conductor Potential Solutions NO CHANGES

17. Work in Progress --- Not for Publication 6 December 2000 17 Challenges Continued development of tools/slurries/pads Cleaning technologies Many new low and high materials - may require new planarization approaches Pattern dependent planarization Planarization over passive elements for SOC Planarization Potential Solutions NO CHANGES

18. Work in Progress --- Not for Publication 6 December 2000 18 Challenges Dimensional control with small features and high A/R Selectivity to etch stops and hard masks Many new low and high materials - may require new chemistries Strip/clean compatibility with these new materials Low damage Etch Potential Solutions NO CHANGES

19. Work in Progress --- Not for Publication 6 December 2000 19 2001 planning Interconnect needs to address novel devices especially vertical devices Performance impact of process induced variation Parametric performance models Can technology metrics be tied to performance limits –Trade-off between low and metal levels and design rules Include crosstalk metric

20. Work in Progress --- Not for Publication 6 December 2000 20 Rapid changes in materials Effect of increase of Cu resistivity at small line widths needs to be calculated Materials solutions alone cannot deliver performance - end of traditional scaling System level solutions must be accelerated Optical/rf/waveguide/3D current alternatives SoC implementations will propagate SoC may change competitive picture - driven by functionality not cost/area Last words