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Alain Espinosa Thin Gate Insulators Nanoscale Silicon Technology PresentersTopics Mike DuffyDouble-gate CMOS Eric DattoliStrained Silicon.

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Presentation on theme: "Alain Espinosa Thin Gate Insulators Nanoscale Silicon Technology PresentersTopics Mike DuffyDouble-gate CMOS Eric DattoliStrained Silicon."— Presentation transcript:

1 Alain Espinosa Thin Gate Insulators Nanoscale Silicon Technology PresentersTopics Mike DuffyDouble-gate CMOS Eric DattoliStrained Silicon

2 Challenges as CMOS feature sizes decrease 1.Carrier Mobility reduction 2.Threshold voltage (V T ) control reduction 3. Off-state leakage increase 4. Power consumption increase

3 A basic MOSFET: Band diagram when on: Eeff

4 Mobility versus technology scaling trend for Intel process technologies. From (Thompson 2004) Problem 1: Carrier Mobility Decreases as Channel length decrease and Vertical Electric fields increase

5 Problem 2: V T Rolloff as Channel length decreases One common solution : Increasing Channel Doping reduces Short Channel Effect Substrate-Strained Silicon Technology: Process Integration H. C.-H. Wang, IEDM 2003

6 (Problem 2) V T Rolloff explained by Short Channel Effect This problem is addressed by Double Gate Technology

7 Problem 3: Tunneling Through Gate Oxide (off state current) This problem is addressed by Strained Silicon, and Thin-Insulator technology Eox

8 Problem 4: Wattage/Area increases as density increases MOSFET Scaling Trends, Challenges, and Potential Solutions Peter M. Zeitzoff and James E. Chung. IEEE CIRCUITS & DEVICES MAGAZINE ¦ JANUARY/FEBRUARY 2005 This problem is addressed by Double Gates, Straining, and thin Gate Insulators

9 Features: Upper and lower gates control the channel region Ultra-thin body acts as a rectangular quantum well at device limits Directly scalable down to 20 nm channel length Double Gate MOSFET

10 Band Structure

11 Type I : Planar Double Gate Type II: Vertical Double Gate Type III: Horizontal Double Gate (FinFET) Layout

12 FinFET Layout

13 Reduced Channel and Gate Leakage Short channel effects are seen in Standard silicon MOS devices DGFET offers greater control of the channel because of the double gate Gate leakage current is prevented by a thick gate oxide

14 Threshold Voltage Control Silicon MOS Transistor: Increased body doping used to control V T for short channel Small number of dopant atoms for very short channel Lowest V T achievable is.5V Double Gate FET : Increased body doping Asymmetric gate work functions (n + / p + gates) Metal gate V T of.1V achievable through work function engineering

15 Increased Carrier Mobility Silicon MOS Transistor: Carrier scattering from increased body doping Transverse electric fields from the source and drain reduce mobility Double Gate FET: Lightly doped channel in a DGFET results in a negligible depletion charge Asymmetric gate: experiences some transverse electric fields Metal gate: transverse electric field negligible with increased channel control

16 Reduced Power Consumption Double Gate coupling allows for higher drive currents at lower supply voltage and threshold voltage Energy is a quadratic function of supply voltage Reduced channel and gate leakage currents in off state translate to huge power savings Separate control of each gate allows dynamic control of V T : Simplified logic gates would save power and chip area

17 Power VS Feature Size

18 Challenges Facing Double Gate Technology 1) Identically sized gates 2) Self-alignment of source and drain to both gates 3) Alignment of both gates to each other 4) Connecting two gates with a low-resistance path

19 Ultimate Double Gate Limits 1) Thermionic emission above the channel potential barrier: Short channel effects lower potential barrier 2)Band-to-band tunneling between body and drain pn junction: Body-drain electric field increases tunneling probability 3) Quantum mechanical tunneling directly between source and drain: Extremely small channel lengths correspond to narrow potential barrier width 4) Other effects of quantum confinement in the thin body

20 Si/Ge Alloys Alloys are uniform crystal structures containing two different materials which posess the same ordering property. Can create Si 1-x Ge x alloys where x is a number from 0.0 to 1.0 This is possible since both materials create diamond type lattices and their lattice constants are close. Lattice constant of alloy is determined by Vegards Law, which is a linear average between the constants of Si and Ge. a alloy = (1-x) a Si + x a Ge Note: other material parameters change: e.g. bandgap Lattice Constants: Si5.431 Angstrom Ge5.658 Angstrom

21 Deviation from Vegards Law (Herzog 1993)

22 A Heterostructure is a semiconductor structure in which the material composition changes with position. Heterostructure devices are made by using Molecular Beam Epitaxy to grow a different material on a substrate. Performance Projections of Scaled CMOS Devices and Circuits With Strained Si-on-SiGe Channels. Jerry G. Fossum, Fellow, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 4, APRIL 2003 Si and Si 1-x Ge x Alloy Heterostructures

23 Physics of Semiconductors and their Heterostructures. Jasprit Singh Si Ge Si Ge

24 Solid State Electronic Devices. Streetman

25 Required to lay heterolayer within a constrained thickness Substrate-Strained Silicon Technology: Process Integration H. C.-H. Wang, IEDM 2003

26 Improved Hot-Electron Reliability in Strained-Si nMOS David Onsongo, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 12, DECEMBER Scale Picture of Strained Si NMOS Heterostructure

27 Process-Strained Si (PSS) CMOS Technology Featuring 3D Strain Engineering C.-H. Ge, IEDM 2003 XYZXYZ Strain Engineering Orientated Wafer Strained-SiGe-Channel p- MOSFET with Enhanced Hole Mobility and Lower Parasitic Resistance v Masashi Shima FUJITSU Sci. Tech. 2003

28 Fabrication and Analysis of Deep Submicron Strained-Si N-MOSFETs Kern (Ken) Rim, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 7, JULY 2000 Biaxial tension in Strained Si on SiGe MOSFET

29 Scaling Planar Circuits IEEE Circuits & Device Magazines Jan/Feb m 0 <.98 m 0 LH HH

30 Rim (2000) Carriers in channel travel along X-Y plane in k-space Z X Y Carriers move along [010] or [100] direction Same Z or [001] Axis in Real Space Applies to common (001) oriented Silicon substrate

31 Carrier mobility is given by: μ n = q t m n * Current Density depends on Carrier mobility: Jx = q n μ n ε x This decrease in carrier mobility is addressed by Strained Silicon. Specifically, well see that m n * is reduced Relationship between effective mass and carrier mobility

32 Channel Structure Design, Fabrication and Carrier Transport Properties of Strained-SYSiGe-On-Insulator (Strained-SOI) MOSFETs S. Takagi+ IEDM 2003 Bonus: Tunneling through Gate Oxide decreases with Strained Silicon

33 Problem To Solve: We will use the WKB Approximation to calculate how much the Gate Tunneling Current is reduced by increasing the insulator/channel barrier height. Remember, Straining increases the insulator/channel barrier height. Transmission Probability depends on m eff, Electric Field across barrier(Eox),and barrier height (Φox)

34 How To Find Si/SiO2 Barrier Height and Eox of Triangular Barrier Eox Unstrained: Φox=3.2 eV Strained: Φox=3.3 eV Device Design for Sub-0.1µm MOSFETs for Sample and Hold Circuits Mayank Kumar Gupta

35

36 Compare 5x difference in Gate Current to difference in Jg (gate current density) at Eox = 8 MV/cm 1/(8 MV/cm) = ln (J unstrained) = ln (J strained) = Their difference is exp(1.7) = 5.5 Which is very close to the theoretical result of 4.7x from the WKB Approximation. This difference isnt constant, at: Eox = 7.4 MV/cm, there is about a 7.5x difference Eox = 9.1 MV/cm, there is about a 4.5x difference

37 Difference in Junstrained/Jstrained as Eox varies is predicted by the theoretical WKB approximation Compares to experimental difference of 4.5x

38 Compares to experimental difference of 7.5x

39 Improved Hot-Electron Reliability in Strained-Si nMOS David Onsongo, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 12, DECEMBER Effects of Eox on Tunneling Current through Gate

40 Better Way to Engineer Strain A 90-nm Logic Technology Featuring Strained-Silicon Scott E. Thompson, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51, NO. 11, NOVEMBER 2004

41 MOSFET Current Drive Optimization Using Silicon Nitride Capping Layer for 65-nm Technology Node. S. Pidin 2004 Symposium on VLSI Tech Digest Strain Applied to NMOSFETs

42 Advantage over Si on SiGe method

43 This method improves Drain Currents for: NMOS PMOS A 90nm High Volume Manufacturing Logic Technology Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors. IEDM 2003

44 SiO 2 limitations Scaling Power Consumption One solution is using High-k dielectric material

45 High-k dielectric material Are used to minimize tunneling current and the out diffusion of boron from the gate. Types 1) 4 < k < 10 ; SiN x 2) 10 < k < 100; Ta 2 O 5, Al 2 O 3, TiO 2 3) 100 < k What we are looking for in High-k dielectrics?

46 One Example of High-k dielectrics Al 2 O 3 I-V Plot for different thicknesses on Si(100)

47 Al 2 O 3 continued Dielectric Constant (k) Recent study show Al 2 O 3 tunneling dielectrics <1nm thick are superior to previously used Si 3 N 4 and SiO 2

48 Some recent of High-k dielectrics Al 2 O 3 film have been used to make 1Gbit DRAM Al 2 O 3 and HfO 2 have been used to produce a Vertical Replacement-gate (VRG) n-Mos.

49 -Conclusions on High-k dielectrics

50 Thank you Questions?

51 Side Problem: Increasing Channel Doping decreases mobility Solid State Electronic Devices. Streetman


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