1. Ch 10 MOSFETs and MOS Digital Circuits
Examine MOSFET use in inverters
Inverter = two transistors in series
Input to gate of driver (at least)
Second transistor acts as load
Output off connection between transistors
NMOS Inverters
Enhancement driver, resistor load
Enhancement driver and load
Enhancement driver, depletion load
CMOS Inverter
N channel driver, P channel load
Analyze to find inverter performance: * Voltage transfer characteristic * Noise margins * Power dissipation * Switching speed
Load
Driver Vo Vi
Ch 10 MOS Digital – Pt. 1

2. MOSFETs and MOS Digital Circuits
Inverters combined in series and parallel to form digital circuits such as AND’s, NAND’s, OR’s, NOR’s, flip- flops, etc.
Understanding inverter operation is basic to understanding and describing digital circuit operation
Also important in modifying their design to enhance their performance, e.g. speed, power dissipation, susceptibility to noise, and fan-out capability
Ch 10 MOS Digital – Pt. 1

3. N-Channel Enhancement MOSFET
Positive voltage on gate attracts electrons to surface to form “induced channel of electrons”.
Channel forms path for electron flow between source and drain.
Without channel, have back-to-back diodes in series between source and drain so negligibly small current
Ch 10 MOS Digital – Pt. 1

4. N-Channel Enhancement MOSFET
Basics of device operation
VTh = threshold voltage
No channel of electrons for vGS < VTh
No current for vGS < VTh
VTh > 0 for enhancement mode n-channel MOSFET
iDS
iDS
Saturation mode operation
(large VDS)
Channel formation
for vGS > VTh
Increasing vGS
Increasing vGS
vDS
vGS
VTh
Ch 10 MOS Digital – Pt. 1

5. N-Channel Enhancement MOSFET
iDS
vDS sat = v GS – VTh
Constant vGS
curve
vDS
Ch 10 MOS Digital – Pt. 1

6. N-Channel Enhancement MOSFET
Cutoff region (vGS < VTh)
Triode region (vDS < vDSsat)
Triode-saturation boundary at vDS = vDSsat = vGS - VTh OR where vGS - vDS = VTh
Saturation region (vDS > vDSsat)
iDS
vDS sat = v GS – VTh
where
vDS
Ch 10 MOS Digital – Pt. 1

7. N-Channel Depletion MOSFET
Basics of device operation
VTh < 0 for depletion mode n-channel MOSFET
VTh = threshold voltage
Channel exists even when no bias is applied to the gate, i.e for vGS = 0.
Drain current can flow for vGS = 0 and for any vGS > VTh.
No channel of electrons for vGS < VTh
No drain current for vGS < VTh
N-type channel
iDS
Saturation mode
operation
vGS
VTh
Ch 10 MOS Digital – Pt. 1

8. N-Channel Depletion MOSFET
iDS
Cutoff region (vGS < VTh)
Triode region (vDS < vDSsat)
Triode-saturation boundary at vDS = vDSsat = vGS - VTh OR where vGS - vDS = VTh
Saturation region (vDS > vDSsat)
vDS sat = v GS – VTh
vGS= 0
vDS
Cutoff
* Only difference from enhancement mode
device is that the gate voltage may be
negative. But vGS must still be larger
than the threshold voltage for the device
to be on!
Ch 10 MOS Digital – Pt. 1

9. N-Channel Enhancement vs Depletion MOSFET
Enhancement MOSFET (VTh > 0 )
Cutoff region (vGS < VTh)
Triode region (vDS < vDSsat)
Triode-saturation boundary at vDS = vDSsat = vGS - VThOR where vGS - vDS = VTh
Saturation region (vDS > vDSsat)
iDS
vDS
vGS < VTh
Depletion MOSFET (VTh < 0 )
iDS
vGS = 0
vDS
Ch 10 MOS Digital – Pt. 1

10. NMOS Inverter (E-MOSFET + Resistor Load)
Analyze to find inverter performance: voltage transfer characteristic, noise margins, power dissipation and switching speed
Transistor characteristics (driver) + + vo vi _ _
Ch 10 MOS Digital – Pt. 1

11. NMOS Inverter - Load Line
Device operation in inverter
Load line comes from connections of transistor in the circuit
For a given vGS, e.g. 3V (=VTh+2V), transistor’s operating point is where load line crosses vGS = 3V transistor characteristic.
Transistor must operate on load line as gate voltage changes.
At points A, the transistor is in cutoff mode (small vGS).
Between points A and C (larger vGS), transistor is in saturation mode.
Between points C and D (even larger vGS), transistor is in triode mode. +
vo = v DS _
iDS
VDD/RD
=5V/2K
=2.5 mA D
Increasing vGS
Load line . A C
vDS
VDD
Ch 10 MOS Digital – Pt. 1

12. NMOS Inverter (E-MOSFET + Resistor Load)
Voltage transfer characteristic
Vo versus Vi
Region I (A to B)
0 < Vi < VTh
iD = 0 since transistor is off, i.e. in cutoff. + + vo vi _ _ vo
iDS A B 5V I
A to B .
vDS vi
VTh=1V 5V
Ch 10 MOS Digital – Pt. 1

13. NMOS Inverter (E-MOSFET + Resistor Load)
Region II (B to C)
Vi > VTh and iD > 0 since transistor is on.
iD is increasing as Vi = vGS increases
Transistor is operating in saturation mode since vDS > vDSsat + + vo vi _ _ vo
iDS
vDSsat A B 5V I II C
A to B C .
vDS vi
VTh =1V 5V
Ch 10 MOS Digital – Pt. 1

14. NMOS Inverter (E-MOSFET + Resistor Load)
Where is point C and what are the corresponding values of Vi and Vo?
At C, transistor is operating at the edge of the saturation mode where + + vo vi _ _
iDS vo A B 5V C I II
A to B . C
1.2V
vDS vi
VTh
2.2V 5V
Ch 10 MOS Digital – Pt. 1

15. NMOS Inverter (E-MOSFET + Resistor Load)
Region III (C to D)
Vi > VTh and iD > 0 since transistor is still on.
Transistor is operating in triode mode so + + vo vi _ _
iDS vo B A
At D, vi = 5V and
vo= 0.95V or
8.7V (not possible). 5V D I II
III C
A to B C .
1.2V D
vDS
0.95V vi
VTh
2.2V 5V
Ch 10 MOS Digital – Pt. 1

16. Noise Margins for NMOS Inverter (E-MOSFET + Resistor Load)
Noise margin for low state
Measures degree of inverter sensitivity to noise for the low state, i.e. how large an input noise signal causes problems at output.
Assumes identical inverter providing input signal
Noise Margin = NML = VIL - VOL where
VOL = output voltage when input set to VOH
VIL = maximum input voltage recognized as a low input
For this inverter design, NML is very low (0.05V) !
Can change by changing R or VTh or transistor’s K.
high
high
low vo
VOH = 5V
NML= VIL - VOL
= 1.0 V V = 0.05 V
VOL=
0.95V vi 5V
VIL=VTh
= 1.0V
Input signal size with noise
that causes problems..
Vi =VOL
= 0.95V
Normal low input signal size without noise.
Ch 10 MOS Digital – Pt. 1

17. Noise Margins for NMOS Inverter (E-MOSFET + Resistor Load)
Noise margin for high state
Measures degree of inverter sensitivity to noise for the high state, i.e. how large a negative input noise signal causes problems at the output.
Assumes identical inverter providing input signal
Noise Margin = NMH = VOH - VIH where
VOH = output high voltage when input set to VOL
VIH = minimum input voltage recognized as a high input
Can change by changing R or VTh or transistor’s K.
How do we find VIH?
low
low
high vo
VOH = 5V
NMH = VOH - VIH
Slope
= -1
VOL= 0.95V 5V vi
Input signal size with noise
that causes problems.
VIH
Vi=VOH
Normal high input signal size without noise.
Ch 10 MOS Digital – Pt. 1

18. Noise Margins for NMOS Inverter (E-MOSFET + Resistor Load)
Noise margin for high state
Noise Margin = NMH = VOH - VIH where
VOH = output high voltage when input set to VOL
VIH = minimum input voltage recognized as a high input
Can find VIH by using expression derived for region II
This VIH is less than 2.2V where FET enters region III, so our guess that device at VIH is in region II is okay.
low
low
high vo
VOH = 5V
NMH = VOH - VIH
= 5 V V
= 3.17 V
Slope
= -1
VOL=
0.95V C
2.2V 5V vi
VIH
Vi=VOH II
III
Ch 10 MOS Digital – Pt. 1

19. Noise Margins for NMOS Inverter (E-MOSFET + Resistor Load)
Alternate analysis for Noise margin for high state
Noise Margin = NMH = VOH - VIH
Can find VIH by using expression derived for region III
The noise margin for the high state NMH now becomes smaller.
NMH = VOH – VIH = 5 V- 4.5 V = 0.5 V
This is smaller than the previously determined value, but is still a factor of ten larger than that for the low state NML = 0.05 V.
low
low
high vo
VOH = 5V
NMH = VOH - VIH
= 5 V- 4.5 V
= 0.5 V
VO= 1.0 V
VOL= 0.95V C
2.2V 5V vi
VIH
VOH II
III
Ch 10 MOS Digital – Pt. 1

20. Power Dissipation for NMOS Inverter (E-MOSFET + Resistor Load)
Input low, output high.
Transistor is off, iD = 0.
Power dissipation PH = 0
Input high (5 V), output low (0.95 V).
Average Static Power Dissipation P + + vo vi _ _
iDS vo A B 5V D I II
III C
A to B C .
1.2V D
vDS
0.95V vi
VTh
2.2V 5V
Ch 10 MOS Digital – Pt. 1

21. Propagation Delays and Switching Times for NMOS Inverters
Previously considered static characteristics of inverters, e.g. Voltage transfer characteristic.
Switching performance is also of interest.
Finite switching times are due to the capacitance load on the output and RC charging and discharging times.
Capacitance load comes from: 1) gate capacitance of subsequent inverters to which the output is connected and 2) capacitance of interconnect wires to inputs of other gates.
Propagation delays
tPHL = output high to low
tPLH = output low to high
tP = (1/2)(tPHL+ tPLH) )
defines the speed of the inverter. + + vo vi _ _ vi t vo t
Ch 10 MOS Digital – Pt. 1

22. Propagation Delays and Switching Times for NMOS Inverters
Load
Output goes from Low to High
Drive transistor turns off
Load resistor provides current to charge up C.
tPLH = time to charge to the midpoint ½(VOH+VOL) = 1/2(5V V) = 3.0V iR iC + C
Driver + vo
vi=VOL
iD= 0 _ _ vo
VDD 3V
tPLH
VOL=
0.95V t
Ch 10 MOS Digital – Pt. 1

23. Propagation Delays and Switching Times for NMOS Inverters
Load
Output goes from High to Low
Drive transistor turns on
But load resistor continues to provide some current so
tPHL = time to discharge from VOH = VDD to
(VOH+VOL) = 1/2(5V V) = 3.0V
vi = VOH iR iC + C
Driver + vo
vi =VOH iD _ _ vo
VDD 3V
tPHL
VOL=
0.95V t
Ch 10 MOS Digital – Pt. 1

24. Propagation Delays Time for NMOS Inverters
Load
Output goes from Low to High
Drive transistor turns off
Load resistor provides current to charge up C.
Output goes from High to Low
Drive transistor turns on to discharge the capacitor but
Load resistor continues to provide current.
Average Propagation Time tPD iR iC + C
Driver + vo
vi=VOL
iD= 0 _ _ vo vo
VDD
VDD 3V 3V
VOL=
0.95V
tPLH
tPHL t
VOL=
0.95V t
Ch 10 MOS Digital – Pt. 1

25. Propagation Delay for NMOS Inverter
Output goes from High (VOH = 5V) to Low (VOL = 0.95V)
Driver transistor Q
(starts from P  R  S  T)
At outset, Q is off (P), and vDS1 = vo = VOH = 5V, vi < VTh
Driver turns on (P to R) when vGS is switched to VOH = 5 V.
Driver initially is in saturation mode, then eventually moves into triode as capacitor discharges and vo (= vDS) decreases
Q moves along constant vGS characteristic (R  S  T).
Ends at (T) in triode region, where vDS = vo = VOL = 0.95V.
Load resistor continuously providing current opposing discharge of capacitor.
Output goes from Low to High
Drive transistor is off (vi = 0.95 V < VTh = 1.0 V
Transistor moves from T  P as the output voltage vo rises to 5 V.
Load iC iR
Driver C iD
Driver
iDS R S
vi = vGS = VOH =5 V T P
vDS
vo=VOL
=0.95V
vo =VOH = 5 V
Ch 10 MOS Digital – Pt. 1

26. Power-Delay Product for NMOS Inverter (E-MOSFET + Resistor Load)
Average Propagation Time tPD
Average Power Dissipation P
Power-Delay Product DP C
* Resistor’s Undesirable Effects
Wasted power for transistor on (output low)
Resistor provides limited charging current
Maximum iR = 2 mA, but iR decreases
as vo rises.
iR slows down discharge of C when
output goes low.
* Problems with this inverter:
* Unequal noise margins!
NML = 0.05 V, NMH = 3.17 V
* Unequal transition times!
τPHL = 4.5 nsec, τPLH = 14 nsec
* Significant power dissipation!
Can we improve on this inverter ?
Ch 10 MOS Digital – Pt. 1