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ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 31 Transistor - Transistor Logic (TTL) iRiR i C3 vivi vovo *TTL basics of operation à Similar to that of.

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Presentation on theme: "ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 31 Transistor - Transistor Logic (TTL) iRiR i C3 vivi vovo *TTL basics of operation à Similar to that of."— Presentation transcript:

1 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 31 Transistor - Transistor Logic (TTL) iRiR i C3 vivi vovo *TTL basics of operation à Similar to that of simplified TTL à Why Q 2 and Q 4 added? à Why the diode D added? *For input low, à Current i R flows out the input (E of Q 1 ) into the output of inverter driving input. à Q 2 is in cutoff since it gets no base current from Q 1. à Q 3 is in cutoff since it gets no base current from Q 2. à Output is high since i C3 ≈ 0. *For input high, à Current i R flows out C of Q 1 into base of Q 2. à Q 2 comes on in active mode and then moves into saturation. à Q 2 ’s emitter current provides base current for Q 3. à Q 3 comes on in active and then moves into saturation mode so output goes low, i.e. v o ≈ V CE,sat = 0.2V.

2 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 32 *Assumptions for analysis: à All transistors are npn and identical. à For p-n junctions in transistors to be conducting current, «V BE or V BC must be 0.7V or higher. «For smaller junction voltages, current flow is negligibly small. à For transistors in forward active mode, «i C = β i B, «V BE,active ≈ 0.7 V à For transistors in forward saturation mode, «V BE,sat ≈ 0.8 V. «V CE,sat ≈ 0.2 V. «i C < β i B or i C / i B < β. à For transistors in inverse mode (E junction reverse biased, C junction forward biased), «current gain is very small «i E = β r i B «β r is very small, e.g. β r ~ 0.02 Transistor - Transistor Logic (TTL) vivi vovo

3 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 33 Transistor - Transistor Logic (TTL) *For input low, i.e. v i = 0.2 V à Current i R = i Ri flows out E of Q 1 into inverter driving the input. à Q 2 is in cutoff since it gets almost no base current. à Q 3 is in cutoff since it gets no base current from Q 2. à Why? à Output is high since i C3 ≈ 0 since Q 3 is off. + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 V B1 v i =V CE,sat = 0.2V + _ i Ri Low Input, High Output vovo i C3 Cutoff

4 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 34 Transistor - Transistor Logic (TTL) + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 V B1 v i =V CE,sat = 0.2V + _ i Ri + _ + _ V BE4 VDVD + _ i R1 off i C2 i B4 R 1 = 1.6 K *For input low, i.e. v i = 0.2 V à Output is high since i C3 ≈ 0 since Q 3 is off. à What is the high output voltage? V CC ? à Look at Q 4 and diode D. à Since Q 2 is off, i C2 ≈ 0 and so i B4 ≈ i R1 à Then we can write à How big is i B4 ≈ i R1 ? à Since Q 3 is off, i C3 ≈ 0 and so i R1 ≈ i B4 ≈ i D ≈ i 0. à For the output high, the next inverter will have its Q 1 ’s emitter junction reverse biased so i 0 ≈ i E1 ≈ 0. à So i B4 ≈ 0, V BE4 ≈ V D = 0.65 V so ioio V CC = 5 V v o = HIGH n p R 3 = 0.13 K weakly on Low Input, High Output iDiD

5 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 35 Transistor - Transistor Logic (TTL) + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 V B1 v i =V CE,sat = 0.2V + _ i Ri + _ + _ V BE4 VDVD + _ i R1 off i C2 i B4 R 1 = 1.6 K *In summary, for input low, i.e. v i = 0.2 V à E junction of Q 1 forward biased, so most of i R flows out of E into collector of driving inverter. à The voltage at the base of Q 1 is low, only 0.2 V + 0.7 V = 0.9 V, so the bias for the three junctions in series is only 0.9 V so V BC1 ≈ V BE2 ≈ V BE3 ≈ 0.3 V, which are too low to conduct. à So Q 2 and Q 3 are in cutoff. à Since output is high and connected to a reverse biased E junction for Q 1 for the following inverter i o ≈ 0 à So i B4 ≈ 0, Q 4 and D are weakly on so V BE4 ≈ V D = 0.65 V. à Very little current is draw by output. à The output voltage is high. i o ≈ 0 V CC = 5 V high n p weakly on R 3 = 0.13 K Low Input, High Output v o = 3.7 V

6 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 36 Transistor - Transistor Logic (TTL) + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 V B1 v i = 3.7V + _ i Ri + _ + _ V BE4 VDVD + _ i R1 on i C2 i B4 R 1 = 1.6 K *For input high, i.e. v i = 3.7 V à Output is low since Q 2 and Q 3 are on. v o = ? à Since input is high, i E1 ≈ 0 so i C1 ≈ i B2 ≈ i Ri. à Then à Since there is current flow out C of Q 1 into base of Q 2 and then into base of Q 3, then à Then à If Q 2 in active mode and β = 10 ioio V CC = 5 V low n p But the base currents for Q 2 and Q 3 are very large and drive these transistors well into saturation. Q 2 cannot be in active mode since i c2 R 1 = (7.3 mA)(1.6K) = 11.7 V >> V CC ! R 3 = 0.13 K High Input, Low Output i B3 i B2 i E2 i R2 vovo i E1 ≈ 0

7 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 37 *For input high, i.e. v i = 3.7 V à Assuming Q 2 and Q 3 are on and in SATURATION. à Then à Then, since Q 2 is in saturation mode, i C2 < β i B2 but V CE2 = 0.2 V and à Then, assuming Q 4 is off, i B4 ≈ 0, à and à So Q 2 and Q 3 are in saturation, and v o = V CE3,sat = 0.2 V. Transistor - Transistor Logic (TTL) + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 V B1 v i = 3.7V + _ i Ri + _ + _ V BE4 VDVD + _ i R1 sat i C2 i B4 R 1 = 1.6 K ioio V CC = 5 V n p i E2 i B3 i R2 i B2 R 3 = 0.13 K High Input, Low Output off V C2 v o = 0.2V R =4 K i Ro = 1.0 mA These verify that Q 2 and Q 3 are in saturation.

8 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 38 Transistor - Transistor Logic (TTL) + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 V B1 v i = 3.7V + _ iRiR + _ + _ V BE4 VDVD + _ i R1 sat i C2 i B4 R 1 = 1.6 K *For input high, i.e. v i = 3.7 V à What about our assumption that Q 4 was off? à Since Q 3 is in saturation, v o = V CE3,sat = 0.2 V. à But we know that at B of Q 4, à So à But we also can write à So, while Q 4 ’s E junction is forward biased, the bias is not enough to cause much current flow. à Here is the reason for the diode. Without the diode, Q 4 would be on since V BE4 = 0.8 V and Q 4 would be in saturation producing a large, undesirable and unnecessary current into Q 3. ioio V CC = 5 V n p i E2 i B3 i R2 i B2 V B4 weakly on R 3 = 0.13 K High Input, Low Output i Ri = 0.65 mA i Ro = 1 mA v o = 0.2 V

9 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 39 Transistor - Transistor Logic (TTL) + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 V B1 v i = 3.7V + _ iRiR + _ + _ V BE4 VDVD vovo + _ i R1 sat i C2 i B4 R 1 = 1.6 K *In summary for input high, i.e. v i = 3.7 V à E junction of Q 1 is reverse biased, so i E1 ≈ 0. à Current i R (~1 mA) flows out C of Q 1 into base of Q 2 forcing Q 2 into the saturation mode. à Most of i E2 goes into base of Q 3 forcing Q 3 into saturation mode à So v o = V CE3,sat = 0.2 V and the output is low. à Q 4 is only weakly on and not providing much current to Q 3 for the output low (0.2 V) and in the static (unchanging) mode. ioio V CC = 5 V n p i E2 i B3 i R2 i B2 V B4 weakly on i E1 R 3 = 0.13 K High Input, Low Output i Ri = 0.65 mA i Ro = 1 mA v o = 0.2 V

10 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 310 Voltage Transfer Characteristic for TTL *Region I (A to B) à For input low, «Current i R flows out E of Q 1 «Q 1 is in saturation since i E1 ≈ i R1 and i C1 ≈ i B2 ≈ 0 «Q 2 is in cutoff since i B2 ≈ 0 «Q 3 is in cutoff since i B3 ≈ 0 «Output is high (3.7 V) since i C3 ≈ 0. à Where is point B? à Recall V B1 = 0.9 V for v i = 0.2 V, so V BC1, V BE2 and V BE3 are too small for current flow. à Q 2 must come on before Q 3 à When does Q 2 come on? à We can write at the onset of Q 2 coming on «V B1 = v i + V BE1 ≈ v i + 0.7 V, «But V B1 ≈ V BC1 + V BE2 since V BE3 ≈ 0. à Assuming Q 2 starts conducting when V BC1 = V BE2 ≈ 0.6 V, « Then v i + 0.7 V = 0.6 V + 0.6 V = 1.2V, « So at point B, v i = 0.5 V + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 = 0 V B1 vivi + _ iRiR vivi vovo AB 0 0 3.7 V V CC = 5 V 0.5 V off i B3 =0 i R2 =0 I R 3 = 0.13 K i B2 =0 i E1 ≈ i R

11 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 311 Voltage Transfer Characteristic for TTL *Region II (B to C) à For v i = 0.5 V, «Q 2 is just turning on so i B2, i C2 ≈ 0 «Q 3 is still in cutoff «Output is high, but starting to decrease. à We can write for v o à Since Q 4 and D are weakly on, V BE4 = V D = 0.65 V so v o is given by à We can approximate i R1 ≈ i C2 so à Since ΔV B2 ≈ Δv i, and V B2 = V BE2 + R 2 i E2, then ΔV B2 = ΔV BE2 + R 2 Δi E2 à Define Δi c2 / ΔV BE2 = 1/r e where r e = dynamic resistance of emitter junction à So ΔV B2 = ΔV BE2 + R 2 Δi E2 ≈ (r e +R 2 ) Δi c2 à So + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 ≈ 0 V B1 vivi + _ iRiR vivi vovo AB 0 0 3.7 V V CC = 5 V 0.5 V V BE4 i R1 off i C2 i B3 ≈ 0 R 1 = 1.6 K C V B2 weakly on II I on i E2 i R2

12 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 312 Voltage Transfer Characteristic for TTL *Region II (B to C) à Where is point C? «Q 2 turned on at B, so Q 2 in active mode so V BE2 = 0.7 V «At C, Q 3 is turning on, so V BE3 ≈ 0.7 V «V B2 = V BE2 + V BE3 = 0.7 V + 0.7 V ≈ 1.4 V «Since Q 1 is in saturation, V CE1 ≈ 0.2 V so v i = V B2 - V CE1 = 1.4V - 0.2V ≈ 1.2V «What is the v o at this point C? «Since for region II we found «then from B to C «and at point C + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 V B1 vivi + _ iRiR vivi vovo AB 0 0 3.7 V V CC = 5 V 0.5V 1.2V V BE4 i R1 on i C2 i B3 R 1 = 1.6 K C V B2 weakly on 2.7 V II I i E2 i R2 v o dropping

13 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 313 Voltage Transfer Characteristic for TTL * Region III (C to D) à Beyond point C, «Q 2 and Q 3 are on «As v i increases, more of i R (~ 1 mA) is directed into base of Q 2, so Q 2 goes into active and then saturation. «Q 2 produces a large current i E2 (~3 mA), and most of it goes into base of Q 3 so Q 3 goes into active and then saturation. à At point D, « Both Q 2 and Q 3 are entering saturation so V B2 = V BE2 +V BE3 = 0.8 V + 0.8 V = 1.6 V. «Since Q 1 is still in saturation,V CE1 ≈ 0.2 V so v i = V B2 - V CE1 = 1.6V - 0.2V = 1.4V «What is the v o at this point D? «Since Q 3 is entering saturation, v o = V CE3,sat = 0.2 V. à So from point C to D, the output drops sharply from 2.7 V to 0.2 V as Q 3 turns on and moves rapidly from active into saturation as the input increases from 1.2 V to 1.4 V. + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 V B1 vivi + _ iRiR vivi vovo AB 0 0 3.7 V V CC = 5 V 0.5V 1.2V 1.4V V BE4 i R1 on i C2 i B3 R 1 = 1.6 K C V B2 weakly on 2.7 V D i E2 sat 0.2 V I II III i R2 v o = dropping

14 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 314 Voltage Transfer Characteristic for TTL *Region IV (D to E) à Beyond point D, «Q 2 and Q 3 are on and are being driven deeper into saturation «As v i increases further, all of i R (~1 mA) is directed into base of Q 2, so Q 2 goes deeply into saturation. «Q 2 produces a large current i E2 (~3 mA), and most goes into base of Q 3 so Q 3 goes deeply into saturation also so v o gets even smaller, i.e v o = V CE3,sat  0.1 V. à So from point D to E, the output drops very slowly from 0.2 V to 0.1 V as the input increases from 1.4 V to 3.7 V. à At point D, the E junction of Q 1 is forward biased and its C junction is forward biased, so Q 1 is still in the forward saturation mode. à At point E, the E junction of Q 1 is reverse biased and its C junction is forward biased, so Q 1 is in the inverse mode. + + + _ + _ _ _ V BE1 V BC1 V BE2 V BE3 V B1 vivi + _ iRiR vivi vovo AB 0 3.7 V V CC = 5 V 0.5V 1.2V 1.4V 3.7 V V BE4 i R1 sat i C2 i B3 R 1 = 1.6 K C V B2 weakly on 2.7 V D i E2 sat 0.2 V 0.1 V I II III EIV i R2

15 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 315 Voltage Transfer Characteristic for TTL *Summary of transfer characteristic à When the input is low, «The current i R goes out the E of Q 1 «So Q 2 and Q 3 get no base current and are off «So the output is high à When the input increases, «Some of i R gets directed into the B of Q 2, so Q 2 gets some base current and comes on in active mode «C current of Q 2 increases, so IR drop across R 1 increases and output voltage drops (B to C) «As Q 2 comes on, it provides base current to Q 3 and Q 3 come on in active mode (C). à When the input increases further, «More of i R gets directed into the C of Q 1, so Q 2 gets more base current and moves into the saturation mode (C to D) «Q 2 provides more base current to Q 3 and then Q 3 moves into saturation mode (D). à Further increases in the input direct all of i R into the C of Q 1, so Q 2 gets even more base current and moves deeper into the saturation mode (D to E). Similarly, Q 3 moves deeper into saturation. vivi + _ vivi vovo AB 0 V OH =3.7 V V CC = 5 V 0.5V 1.2V 1.4V 3.7 V V IL V IH C 2.7 V D V OL = 0.1 V I II III EIV iRiR R 3 = 0.13 K Q 2 comes on Q 3 comes on, Q 2 heads towards saturation Q 3 reaches saturation, Q 2 already in saturation Q 1 comes out of saturation Q 1 in saturation, Q 2 and Q 3 off

16 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 316 Voltage Transfer Characteristic for TTL *Noise Margins à Noise Margin for low state NM L = V IL -V OL «V OL = low output voltage for typical high input voltage = 0.1 V «V IL = maximum input voltage recognized as a low input = 0.5 V «NM L = V IL -V OL = 0.5 V - 0.1 V = 0.4 V à Noise Margin for high state NM H = V OH -V IH «V OH = high output voltage for typical low input voltage = 3.7 V «V IH = minimum input voltage recognized as a high input = 1.4 V «NM H = V OH -V IH = 3.7 V - 1.4V = 2.3 V à Noise margins are very unequal for this technology. «Noise margins are similar to simplified TTL and RTL cases. «Noise margins cannot be easily changed. vivi + _ vivi vovo AB 0 V OH =3.7 V V CC = 5 V 0.5V 1.2V 1.4V 3.7 V V IL V IH C 2.7 V D V OL = 0.1 V I II III E IV iRiR NM H NM L vovo


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