1. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 21 Simplified Transistor - Transistor Logic (TTL) *Transistor - Transistor Logic (TTL) *Simplified form of inverter à Two instead of four transistors à Two instead of four resistors *For low v i input, output v o is high à Q 1 is on (saturation). à Q 3 is off (cutoff). à So v o = V CC - i C R C ≈ V CC *For high v i input, output v o is low à Q 1 is off (inverse mode). à Q 3 is on (saturation). à So v o = V CC - i C3 R C is small. à Q 3 driven into saturation region so v o = V CE,sat ≈ 0.2V. vivi vovo + iRiR

2. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 22 Simplified Transistor - Transistor Logic (TTL) *Assumptions for analysis: à All transistors are npn and identical. à For p-n junctions in transistors to be conducting current, «V BE or V BC must be 0.7V or higher. «For smaller junction voltages, current flow is negligibly small. à For transistors in forward active mode, «i C = β i B, «V BE,active ≈ 0.7 V à For transistors in forward saturation mode, «V BE,sat ≈ 0.8 V. «V CE,sat ≈ 0.2 V. «i C < β i B or i C / i B < β. à For transistors in inverse mode (E junction reverse biased, C junction forward biased), «current gain is very small «i E = β r i B «β r is very small, e.g. β r ~ 0.02 vivi vovo

3. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 23 Simplified Transistor - Transistor Logic (TTL) *For low v i input, output v o is high *Q 3 of driving inverter is in saturation so v o = V CE,sat = 0.2 V = v i of Q 1 *Transistor Q 1 (Load Inverter) à E jcn forward biased (V BE1 = 0.7 V ). à C jcn only weakly forward biased (V BC1 = ? ). à Q 1 in saturation (V CE1 = V CB1 + V BE1 = -V BC1 + V BE1 ≈ -0.45V + 0.7V = 0.25V) and i C1 < β i B1. *Transistor Q 3 (Load Inverter) à How do we find V BC1 ? à V B1 = V BC1 + V BE3 = 0.9 V à Assuming V BC1 ≈ V BE3, then both = 0.45 V à So E jcn of Q 3 forward biased, but not enough so i B3 ≈ 0 and Q 3 is off (i C3 ≈ 0). à R C i C3 ≈ 0 and v o ≈ V CC = 5 V. *Current i R flows through R and out the input à Size of i R ? i R = (V CC - V B1 )/R = (5 V - 0.9 V)/4K=1 mA à Where does it go? à Virtually all of the current flows out emitter of Q 1, i R ≈ i E1 = 1mA à This current flows into the collector of Q 3. of the drive inverter (out the input). vovo + v o =V CE,sat = 0.2 V Q 3 in saturation Driving inverter n p n n n p + + + + V BE1 = 0.7V V B1 = 0.7V+0.2V = 0.9V. V BC1 V BE3 V CC = 5V iRiR R=4K i E1 V I 0.7 V Low Input, High Output i C1 Load inverter

4. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 24 Simplified Transistor - Transistor Logic (TTL) *Q 3 in driving inverter is in cutoff so v o = V CC = 5 V = v i of Q 1 *Transistor Q 1 (Load Inverter) à E jcn rev. biased (V BE1 = 0.7V, V BE1 < 0). à C jcn forward biased (V BC1 = ? ). à Q 1 in inverse active mode and i E1 = β r i B1 ≈ 0, since β r is very small, e.g. β r ~ 0.02 *Transistor Q 3 (Load Inverter) à How do we find V BC1 ? à Know V B1 = V BC1 + V BE3 à Assuming i R flows through C junction of Q 1 and into the base of Q 3, then V BC1 ≈ V BE3 ≈ 0.7 V so i R = (V CC - V BC1 -V BE3 )/R = (5 V- 1.4 V)/4K = 0.9 mA à So E jcn of load’s Q 3 is forward biased, i B3 ≈ i R = 0.9 mA = 900 µA! à If Q 3 in active mode, i C3 = β i B3 and for β = 50, then i C3 = 50(0.9 mA) = 45 mA. à Is this possible? NO! Why? v o = V CC - i C3 R C = 5 V - 45 mA (1.6K) = 5V - 72V = - 67V < 0 ! Not possible ! à So Q 3 must be in saturation mode since the base current is very large (900 µA), where v o = V CE,sat ≈ 0.2 V; so i C3 =(5V-0.2V)/1.6K= 3mA. This verifies that Q 3 is in saturation since i C3 = 3 mA < β i B3 = 45 mA. vovo + v o =V CC = 5 V Q 3 in cutoff Driving inverter n p n n n p + + + + V BE1 < 0 V B1 = 5 V-i R R. V BC1 V BE3 V CC = 5V iRiR R=4K i C1 ≈ i B3 V I 0.7 V R C = 1.6K active Saturation i C /i B <  i E1 ≈ 0 I c3 = 3 mA High Input, Low Output v CE iCiC

5. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 25 Simplified TTL Transfer Characteristic *Region I (A to B) (Low v i, high v o ) *Q 1 is in forward saturation à E jcn forward biased (V BE1 = 0.7 V and base current is large, i B1 = i R1 = 1 mA ). à C jcn is weakly forward biased (V BC1 = 0.45 V ), so Q 1 in saturation mode. à V CE1 = V CB1 +V BE1 = -V BC1 +V BE1 ≈ -0.45 + 0.7 ≈ 0.25V à Current i R is flowing out the input. *Q 3 is biased in forward active mode, but only weakly (not on since V BE3 < 0.7 V). à V B1 = v i + 0.7 V à Assuming V BC1 ≈ V BE3, then both are equal to (0.35 V + v i /2) ~ 0.45V < 0.7 V. à So E jcn of Q 3 is forward biased, but not enough so i B3 ≈ 0 and Q 3 is off. à Then i C3 ≈ 0 and v o ≈ V CC = 5 V. *Note à i R = (V CC – V CE3,sat –V BE1 )/R = (5 V - 0.2V - 0.7V)/4K = 1.0 mA à Since i C1 = i B3 ≈ 0, nearly all of this current is going out the E of Q 1 so i E1 ≈ i R = 1.0 mA. vovo + vivi n p n n n p + + + + V BE1 = 0.7V V B1 = 0.7V+v i. V BC1 V BE3 V CC = 5V iRiR R=4K i E1 vivi vovo V CC = 5V BA i C1 = i B3 i C3 I R C = 1.6K

6. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 26 Simplified TTL Transfer Characteristic *Region II (B to C) (Transition region) *Q 1 is still in saturation. *Q 3 initially is biased in forward active mode, but weakly (V BE3 < 0.7 V). à When does this change? à When v i = 0.6 V, then V B1 = v i + 0.7 V = 1.3 V so V BC1 ≈ V BE3 = 0.65 V and these p-n junctions can begin to conduct current. à This current comes thru R as i R. à This provides the base current for Q 3 to begin to turn on and so the collector current i C3 rises and the output voltage starts dropping according to v o = V CC - i C3 R C = 5 V - i C3 (1.6K) *Note the size of i R is about the same as before, i.e. i R = (V CC - V BC1 -V BE3 )/R = (5 V- 1.3 V)/4K = 0.93 mA. Most of this current is still going out the gate input (E of Q 1 ) since i B3 starts out very small (~μA’s). + vivi n p n n n p + + + + V BE1 = 0.7V V B1 = 0.7V+v i. V BC1 V BE3 V CC = 5V iRiR R=4K i E1 vivi vovo 0.6 V 0.7V V CC = 5V BA -i C1 = i B3 i C3 C V CE3,sat = 0.2V III vovo R C = 1.6K

7. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 27 Simplified TTL Transfer Characteristic *Region II (B to C) (Transition region) *Q 1 initially in saturation *Q 3 initially is biased in forward active mode, but only weakly on since V BE3 < 0.7 V. à For Q 3, as v i rises, the base current i B3 rises, i C3 rises and the output voltage drops. v o = V CC - i C3 R C = 5 V - i C3 (1.6K) *Where is point C? à When v i = 0.7 V, then V B1 = V BC1 + V BE3 = v i + 0.7 V = 1.4 V so V BC1 ≈ V BE3 = 0.7 V and these p-n jncs can conduct large currents. à As v i rises from 0.6 V to 0.7 V, more and more of i R (0.9 mA) goes into the base of Q 3 and it enters further into the active mode. *At C, Q 3 reaches the edge of saturation, v o = V CE,sat = 0.2 V, so i C3 = (5V - 0.2)/1.6K = 3 mA. Then i B3 = i C3 /β = 3mA/50 = 60 μA. So only 60 μA of i R (~ 1 mA = 1000 μA) needs to be diverted into the base of Q 3 to drive it into saturation! *So at point C most of i R is still going out the gate’s input (E of Q 1 ), since i R = 0.9 mA and i B3 = 60 μA. vovo + vivi n p n n n p + + + + V BE1 = 0.7V V B1 = 0.7V+v i. V BC1 V BE3 V CC = 5V iRiR R=4K i E1 vivi vovo 0.6 V 0.7V V CC = 5V BA -i C1 = i B3 i C3 C V CE3,sat = 0.2V I II active Saturation i C /i B < β A,B C Q3Q3 R C = 1.6K *Where is point C? v CE iCiC

8. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 28 Simplified TTL Transfer Characteristic *Region III (C to D) (Low output region) *Q 1 initially still in saturation at C à As v i rises above 0.7V, V B1 is nearly constant at 1.4V, so E junction of Q 1 becomes less forward biased and then eventually becomes reverse biased. à C junction is forward biased, so Q 1 moves from forward active to inverse active mode where i E1 = β r i B1 where β r = 0.02 << β = 50. *Q 3 is entering saturation at C, V BE3 ≈ 0.7 V à For Q 3, as v i rises above 0.7 V, V B1 rises slowly to 1.6 V as v i rises to 5 V. à When V B1 ≈ 1.6 V, then V BC1 ≈ V BE3 = 0.8 V = V BE.sat. à At V BE3 = 0.8 V, i B3 is larger yet and now Q 3 is strongly driven into saturation so V CE3,sat  0.1 V. à For Q 3 in saturation, i C3 << β i B3. As i B3 increases, i C3 is nearly constant since v o = V CE3,sat and V CE3,sat goes down from 0.2 V to 0.1 V so iC3 increases from 3.0 mA to i C3 = (5V - 0.1)/1.6K = 3.06 mA. vovo + vivi n p n n n p + + + + V BE1 V B1 ≈ 1.4V. V BC1 V BE3 V CC = 5V iRiR R=4K i E1 vivi vovo 0.6 V 0.7V 5 V V CC = 5V BA i C1 = i B3 i C3 C 0.2V 0.1V I II active Saturation i C /i B < β A,B C Q3Q3 D III D R C = 1.6K v CE iCiC

9. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 29 Simplified TTL Transfer Characteristic *Noise Margin (Low state) à V OL = V CE3,sat = 0.1 V à V IL = 0.6 V à NM L = V IL - V OL = 0.6V - 0.1 V = 0.5 V *Noise Margin (High state) à V OH = V CC = 5 V à V IH = 0.7 V à NM H = V OH - V IH = 5 V - 0.7 V = 4.3 V vovo + vivi + + + V BE1 V BC1 V BE3 V CC = 5V R=4K vivi vovo 0.6V 0.7V 5 V V CC = 5V BA C 0.2V V OL = 0.1V III active Saturation i C /i B < β A,B C Q3Q3 D III D. R C = 1.6K + NM H = V OH - V IH V OL V IL V IH V OH NM L = V IL - V OL v CE iCiC

10. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 210 Simplified TTL Propagation Delay *Output going high à Transistor Q 3 turned off (cutoff) à Charging current flows through R C à t PLH is time it takes the output to rise from V OL = V CE,sat = 0.1 V to 1/2(V OH + V OL ) = 2.6 V V CE + V BE + B vovo V OH = 5V V OL =0.1V V IL C vovo + i Cap i Rc t vovo V CC V CE,sat V CC = 5 V vivi 0.6 V 0.7V 5 V A C III D III V IH R C = 1.6K t PLH

11. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 211 Simplified TTL Propagation Delay V CE + V BE + B vovo V OH = 5V V OL =0.1V V IL C vovo + i Cap i Rc t vovo V CC V CE,sat V CC = 5 V vivi 0.6 V 0.7V 5 V A C III D III *Output going low à Transistor Q 3 turned on (initially active, moving toward saturation) and providing discharge current (P  R  S) à But current also flows through R C à t PHL is time it takes the output to fall from V OH = V CC = 5 V to 1/2(V OH + V OL ) = 2.6 V P R S V IH R C = 1.6K t PHL v CE iCiC 2.6 V

12. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 212 Simplified TTL Propagation Delay V CE + V BE + C vovo + i Cap i Rc t vovo V CC V CE,sat V CC = 5 V P RS *Output going low iCiC R C = 1.6K What current to use for the transistor Q 3 ? v CE iCiC t PHL 2.6 V

13. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 213 *Output going low à Q 3 starts in active mode at Pt. R à Final note: «i C = 45 mA is a very large current, which is useful for discharging the capacitor quickly. «When the capacitor is discharged, this i C3 drops dramatically in size to only «At this point, Q 3 is now in saturation mode since Simplified TTL Propagation Delay V CE + V BE + C vovo + i Cap i Rc t vovo V CC V CE,sat V CC = 5V P RS i B3 i C3 iRiR R C = 1.6K v CE iCiC

14. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 214 Simplified TTL Power Dissipation V CE + V BE + B vovo V OH = 5V V OL =0.1V V IL C vovo + i Cap iRiR V CC = 5 V vivi 0.6 V 0.7V 5 V A C III D III V IH *Output High State à Transistor Q 3 is in cutoff so i C3 = 0, so no static power dissipation in Q 3. à Transistor Q 1 is in saturation with i B1 = i R = 1 mA à Static power dissipation for high state, P L1 =V CC i R = (5 V)(1 mA) = 5 mW à So static power dissipation for the inverter for the high output state is P H = 5 mW *Output Low State à Transistor Q 3 is in saturation so v o = V CE,sat = 0.1 V. à i C3 = (V CC - V CE3,sat )/R C = (5V - 0.1 V)/1.6K = 3 mA. à P L3 =V CC i C3 = (5 V)(3 mA) = 15 mW à Transistor Q 1 is in the inverse active mode, but still has a large base current of 0.9 mA. à P L1 =V CC i R = (5 V)(0.9 mA) = 4.5 mW à Total power dissipation in low state P L =19.5 mW à Average P = 1/2(P H + P L ) = 12.3 mW *Power - Delay Product à DP = P t p =(12.3 mW)(8.3 nsec) = 102 pJ i C3 R C = 1.6K

15. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 215 Simplified Transistor - Transistor Logic *Simplified TTL provides performance similar to RTL. Logic levels and noise margins à Noise Margin for Low State «NM L = V IL – V O = 0.6 V - 0.1 V = 0.5 V à Noise Margin for High State «NM H = V OH - V IH = 5 V - 0.7 V = 4.3 V à Unequal noise margins for high and low states. *Propagation delays à Output going low à Output going high à Propagation delay *Power – Delay Product * Simplified TTL very similar to RTL in noise margins. * Better speed due to smaller R C used in simplified TTL (1.6 K) versus 10 K in RTL. * Simplified TTL worse in power dissipation and power-delay product. * Also more costly and complex due to use of more transistors per gate.

16. ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 216 Simplified TTL vs. RTL *Logic levels and noise margins à Noise Margin for Low State «NM L = V IL – V O = 0.6 V - 0.1 V = 0.5V à Noise Margin for High State «NM H = V OH - V IH = 5 V - 0.7 V = 4.3 V à Unequal noise margins for high and low states. *Propagation delays à Output going low à Output going high à Propagation delay *Power – Delay Product *Logic levels and noise margins à Noise Margin for Low State «NM L = V IL – V O = 0.7 V - 0.2 V = 0.5 V à Noise Margin for High State «NM H = V OH - V IH = 5 V - 0.8 V = 4.2 V à Unequal noise margins for high and low states. *Propagation delays à Output going low à Output going high à Propagation delay *Power – Delay Product vivi vovo vivi vovo