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ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Lecture 28 Field-Effect Transistors.

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Presentation on theme: "ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Lecture 28 Field-Effect Transistors."— Presentation transcript:

1 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Lecture 28 Field-Effect Transistors

2 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Field-Effect Transistors 1.Understand MOSFET operation. 2. Analyze basic FET amplifiers using the load- line technique. 3. Analyze bias circuits.

3 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. 4. Use small-signal equivalent circuits to analyze FET amplifiers. 5. Compute the performance parameters of several FET amplifier configurations. 7. Understand the basic operation of CMOS logic gates.

4 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. NMOS Transistor

5 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. NMOS Transistor

6 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation in the Cutoff Region

7 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation Slightly Above Cut-Off By applying a positive bias between the Gate (G) and the body (B), electrons are attracted to the gate to form a conducting n-type channel between the source and drain. The positive charge on the gate and the negative charge in the channel form a capacitor where:

8 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. The amount of negative charge that accumulates in the channel is given by: This amount of charge is able to move a distance L from the source to the drain in a time  given by: Operation Slightly Above Cut-Off

9 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. The initial current flow for low drain-source voltage is given by: Operation Slightly Above Cut-Off

10 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation Slightly Above Cut-Off For small values of v DS, i D is proportional to v DS. The device behaves as a resistance whose value depends on v GS.

11 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation in the Triode Region

12 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Operation in the Saturation Region

13 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.

14 Exercise 12.1 Consider an NMOS transistor having V to =2V. What is the region of operation (triode, saturation, or cutoff) if: 1. v GS = 1V and v DS = 5V? Cutoff since v GS V to and v DS V to and v DS >v GS – V to 4.v GS = 5V and v DS = 6V? Saturation since v GS >V to and v DS >v GS - V to

15 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.2 Suppose that we have an NMOS transistor with KP = 50  A/V 2, V to = 1V, L = 2  m and W = 80  m. Sketch the drain characteristics for v DS from 0 to 10V and v GS =0, 1, 2, 3 and 4V. For v GS = 0 or 1V, the transistor is cutoff and the drain current is zero. In the saturation region: The boundary between the triode and saturation regions occurs when

16 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.2

17 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. PMOS Transistor p+ n

18 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. MOSFET Summary

19 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.3 Suppose that we have an PMOS transistor with KP = 25  A/V 2, V to = -1V, L = 2  m and W = 200  m. Sketch the drain characteristics for v DS from 0 to -10V and v GS = 0, -1, -2, -3 and -4V. For v GS = 0 or -1V, the transistor is cutoff and the drain current is zero. In the saturation region: The boundary between the triode and saturation regions occurs when

20 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.3

21 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit

22 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. To establish the load line, we first locate two points on it: Load-Line Analysis of a Simple NMOS Circuit For v DD = 20V and R D =1k 

23 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit

24 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit The quiescent operating point (Q point) is found for v in = 0V

25 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit The maximum gate-to-source voltage is found for v in = 1V

26 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit The minimum gate-to-source voltage is found for v in = -1V

27 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit

28 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Peak to peak swing of v GS is 2V Peak to peak swing of v DS is 12V

29 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. The output is not proportional to the input. The output goes down by 7V for a change of +1V on the input. The output goes up by 5V for a change of -1V on the input. The output is said to be “distorted”. This is due to the uneven spacing of the characteristic curves. v DSQ =11V +5V -7V

30 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Load-Line Analysis of a Simple NMOS Circuit Uneven spacing of the drain characteristics

31 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.4 Find v DSQ, v DSmin and v DSmax if the circuit values are changed to V DD =15V, V GG =3V: 3V 15V

32 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. To establish the load line, we first locate two points on it: For v DD = 15V and R D =1k  Exercise 12.4

33 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Exercise 12.4 v DSQ =11V v DSmin =6Vv DSmax =14V

34 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. FET Logic

35 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. CMOS Inverter

36 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Two-Input CMOS NAND Gate

37 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc. Two-Input CMOS NOR Gate

38 ELECTRICAL ENGINEERING: PRINCIPLES AND APPLICATIONS, Fourth Edition, by Allan R. Hambley, ©2008 Pearson Education, Inc.


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