ISLAMIC UNIVERSITY OF GAZA Faculty of Engineering Computer Engineering Department EELE3321: Digital Electronics Course Asst. Prof. Mohammed Alhanjouri.
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ISLAMIC UNIVERSITY OF GAZA Faculty of Engineering Computer Engineering Department EELE3321: Digital Electronics Course Asst. Prof. Mohammed Alhanjouri Lecture 1: Properties and Definitions of Digital ICs Spring 2009-2010
Digital electronics circuits are represented by five basic logic operations: NOT (Inverter) AND OR NAND NOR
NOT (inverter) inputOutput 10 01 AND InputOutput aby 000 010 100 111 OR InputOutput aby 000 011 101 111 NAND InputOutput aby 001 011 101 110 NOR InputOutput aby 001 010 100 110 The truth table is a table to represent the relation between the input and the output Inverting and Non-Inverting (Buffer)
IDEAL LOGIC ELEMENTS Ideal Inverter One power supply (V cc ) typical operating voltage of many logic families is 5V I cc is zero (ideal) P cc is zero (ideal) – power dissipated Vin < Vcc/2 Vout is logical 1 (Vcc) Vin > Vcc/2 Vout is logical 0 Vin = Vcc/2 Unpredictable results (Should be avoided) CMOS logic family is the nearest to ideal Voltage Transfer Characteristic Transient Response
Ideal input and output Gate Impedances Model of the input and the output impedance of a logic inverter For multiple output (referred to as Fan-out) the logic gates is directly dependent upon the gate’s input and output impedances
Static driving of Multiple (Identical) Inverters I out = N Í in For very large input resistance, the input current is zero, and the driving capabilities are maximized. Ideally, the infinite input resistance is desired because given infinite driving capability.
But for cascaded inverters with infinite input resistance the input capacitance of load gates must be charged through the output resistance of driving inverter For small output resistance the charging current is large and faster switching time Zero output resistance, for ideally For small capacitance, faster switching when fewer gates
Inverting Voltage transfer characteristics V OH = Output High Voltage V m = Midpoint Voltage V OL = Output Low Voltage V IH = Input High Voltage V IL = Input Low Voltage V TW = Transition Width = V IH – V IL V LS = Logic Swing Voltage = V OH – V OL At V m V in = V out
Noise in Digital Circuits Noise Margins: High noise Margin V NMH =V OH – V IH Low noise Margin V NML =V IL – V OL Noise Sensitivities: High noise Sensitivity V NSH =V OH – V m Low noise Sensitivity V NSL =V m – V OL Noise Immunities: Is the ability of a gate to reject the noise High noise Immunity V NIH = V NSH /(V OH – V OL ) Low noise Immunity V NIL = V NSL /(V OH – V OL ) (V OH – V OL )= V LS V OH V IH Undefined Region V IL V OL “1” “0”
Fan-In and Fan-Out The maximum Fan-out possible during the driving gate’s logical “1” output state is The maximum Fan-out possible during the driving gate’s logical “0” output state is The maximum Fan-out possible is the smallest value. The maximum Fan-out possible is an Integer number. If the Maximum Fan-out is not integer, should be use Integer number less than the actual value.
Transient Characteristics Digital logic circuits have finite switching speeds Propagation delay When the input voltage changes from one level to another, the output voltage response is delayed in time
V OH < V cc t d = delay time t r = rise time t s = storage time t f = fall time t ON = t d +t r = turn on time t OFF = t s +t f = turn off time t r and t f are associated with charging and discharging load capacitance t d and t s are associated with stored charge of PN Junction Switching Speed Definitions
Propagation Delay Times t PLH = low to high propagation delay time t PHL = high to low propagation delay time t p (ave.) = (t PLH + t PHL ) / 2
Power Dissipation We have two power dissipated values P cc (OH) output high P cc (OL) output low The average power dissipation But for some logic circuit as shown, the power equations as:
Power-delay product For faster propagation delay times, the power dissipation will be increase, while the lower power dissipation results in longer propagation delay times. Power-delay product = Speed-power product PD = P Diss (ave)*t P (ave) (Joules) Homework of Ch.1 From chapter 1 problems, try to solve the following problems 1.3, 1.12, 1.18, 1.26 Then submit your solutions for course discussion teacher.