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Lecture 10 Metal-Oxide-Semiconductor (MOS) Field-Effect Transistors (FET) MOSFET Bias Analysis.

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Presentation on theme: "Lecture 10 Metal-Oxide-Semiconductor (MOS) Field-Effect Transistors (FET) MOSFET Bias Analysis."— Presentation transcript:

1 Lecture 10 Metal-Oxide-Semiconductor (MOS) Field-Effect Transistors (FET) MOSFET Bias Analysis

2 Goals Investigate circuits that bias transistors into different operating regions. Two Supplies Biasing Four Resistor Biasing Two Resistor Biasing Biasing using Current Mirror Understand Bias Point Stability Investigate DC Analysis for P-Channel Transistor

3 Bias Analysis Approach Assume an operation region (generally the saturation region) Use circuit analysis to find V GS Use V GS to calculate I D, and I D to find V DS Check validity of operation region assumptions Change assumptions and analyze again if required. NOTE :An enhancement-mode device with V DS = V GS is always in saturation

4 Bias Analysis of n-channel MOSFET Check V GS V GS < V TN Cutoff region i D =0 V GS > V t V DS < V GS –V TN Triode region V DS > V GS –V TN Sat. region we start the analysis by assuming certain operating region

5 Example-1 Biasing using two voltage supplies for gate and drain terminal

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7 Example 2 ( Biasing in Triode Region) Assumption: I G =I B =0, transistor is saturated (since V DS= V GS ) Analysis: V GS =V DD =4 V Also But V DS

8 Four-Resistor and Two-Resistor Biasing Provide excellent bias for transistors in discrete circuits. Stabilize bias point with respect to device parameter and temperature variations using negative feedback. Use single voltage source to supply both gate-bias voltage and drain current. Generally used to bias transistors in saturation region. Two-resistor biasing uses lesser components that four- resistor biasing and also isolates drain and gate terminals

9 Bias Analysis: Example3 (Four-Resistor Biasing) Problem: Find Q-pt (I D, V DS ) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region Assumption: Transistor is saturated, I G =I B =0 Analysis: First, simplify circuit, split V DD into two equal-valued sources and apply Thevenin transformation to find V EQ and R EQ for gate-bias voltage

10 Bias Analysis: Example 3 (Four-Resistor Biasing) (contd.) Since I G =0, Since V GS V GS -V TN. Hence saturation region assumption is correct. Q-pt: (34.4 A, 6.08 V) with V GS = 2.66 V

11 Two Resistor Biasing Biasing the MOSFET using a large drain-to-gate feedback resistance, R G. V DD > V t MOS is ON and always in saturation (diode connected transistor)

12 Bias Analysis: Example 4 (Two-Resistor Biasing) Assumption: I G =I B =0, transistor is saturated (since V DS= V GS ) Analysis: Since V GS V GS -V TN. Hence saturation region assumption is correct. Q-pt: (130 A, 2.00 V)

13 Additional Biasing Circuits_2 Using constant current source

14 How to implement a current source (Current mirrors) For Q 1 For Q 2

15 N-branch current mirror I ref I1I1 I2I2 InIn W/L (W/L) 1 (W/L) 2 (W/L) n

16 n-channel and P-Channel MOSFETs

17 DC –Analysis of P-channel MOS Note: The direction of current is out of the drain for a PMOS

18 Bias Analysis: Example 5 (Two-Resistor biasing for PMOS Transistor) Assumption: I G =I B =0, transistor is saturated (since V DS= V GS ) Analysis: Also Since V GS = V is less than V TP = -2 V, V GS = V I D = 52.5 A and V GS = V Hence saturation assumption is correct. Q-pt: (52.5 A, V)

19 Example The circuit below uses a p-channel enhancement MOSFET with k(W/L) = 2 mA/V 2 and V t = -1 V. Find the value for R that produces V 0 = 10 V.

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21 Modifications to Drain Current Equations Channel-Length Modulation Increasing v DS beyond v DSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by ΔL). Effect of v DS on i D in the saturation region. The MOSFET parameter V A depends on the process technology and, for a given process, is proportional to the channel length L. It can be called; channel length modulation (λ), or Early voltage (V A )

22 Example A saturated MOSFET is operated with a constant v GS. The drain current, i D, is found to be 2 mA for v DS = 4 V and 2.2 mA for v DS = 8 V. Find the values of V A, λ and r o.

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24 Including the effect of Channel Length Modulation in the MOSFET model (Valid in the Saturation region) Output resistance

25 Rs V GS iDiD Rs V t1 V t2 Variations in K(W/L) Variation in V t VGVG iDiD RSRS V GS =V G -i D R S Bias-Point Stability for MOS Amplifiers (source degeneration) Large R s stable bias point but requires large supply voltage R s is called degeneration resistance


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