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**Lecture 10 Metal-Oxide-Semiconductor (MOS) Field-Effect Transistors (FET) MOSFET Bias Analysis**

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Goals Investigate circuits that bias transistors into different operating regions. Two Supplies Biasing Four Resistor Biasing Two Resistor Biasing Biasing using Current Mirror Understand Bias Point Stability Investigate DC Analysis for P-Channel Transistor

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**Bias Analysis Approach**

Assume an operation region (generally the saturation region) Use circuit analysis to find VGS Use VGS to calculate ID, and ID to find VDS Check validity of operation region assumptions Change assumptions and analyze again if required. NOTE :An enhancement-mode device with VDS = VGS is always in saturation

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**Bias Analysis of n-channel MOSFET**

Check VGS we start the analysis by assuming certain operating region VGS> Vt VGS< VTN VDS < VGS –VTN Triode region VDS > VGS –VTN Sat. region Cutoff region iD=0

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Example-1 Biasing using two voltage supplies for gate and drain terminal

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**Example 2 ( Biasing in Triode Region)**

Also But VDS<VGS-VTN. Hence, saturation region assumption is incorrect Using triode region equation, Assumption: IG=IB=0, transistor is saturated (since VDS= VGS) Analysis: VGS=VDD=4 V and ID=1.06 mA VDS<VGS-VTN, transistor is in triode region Q-pt:(1.06 mA, 2.3 V)

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**Four-Resistor and Two-Resistor Biasing**

Provide excellent bias for transistors in discrete circuits. Stabilize bias point with respect to device parameter and temperature variations using negative feedback. Use single voltage source to supply both gate-bias voltage and drain current. Generally used to bias transistors in saturation region. Two-resistor biasing uses lesser components that four-resistor biasing and also isolates drain and gate terminals

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**Bias Analysis: Example3 (Four-Resistor Biasing)**

Assumption: Transistor is saturated, IG=IB=0 Analysis: First, simplify circuit, split VDD into two equal-valued sources and apply Thevenin transformation to find VEQ and REQ for gate-bias voltage Problem: Find Q-pt (ID, VDS) Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region

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**Bias Analysis: Example 3 (Four-Resistor Biasing) (contd.)**

Since VGS<VTN for VGS= V and MOSFET will be cut-off, and ID= 34.4 mA Also, Since IG=0, VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (34.4 mA, 6.08 V) with VGS= 2.66 V

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Two Resistor Biasing Biasing the MOSFET using a large drain-to-gate feedback resistance, RG. VDD> Vt MOS is ON and always in saturation (diode connected transistor)

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**Bias Analysis: Example 4 (Two-Resistor Biasing)**

Since VGS<VTN for VGS= V and MOSFET will be cut-off, Assumption: IG=IB=0, transistor is saturated (since VDS= VGS) Analysis: and ID= 130 mA VDS>VGS-VTN. Hence saturation region assumption is correct. Q-pt: (130 mA, 2.00 V)

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**Additional Biasing Circuits_2 Using constant current source**

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**How to implement a current source (Current mirrors)**

For Q1 For Q2

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**N-branch current mirror**

Iref I1 I2 In W/L (W/L)1 (W/L)2 (W/L)n

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**n-channel and P-Channel MOSFETs**

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**DC –Analysis of P-channel MOS**

Note: The direction of current is out of the drain for a PMOS

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**Bias Analysis: Example 5 (Two-Resistor biasing for PMOS Transistor)**

Also Since VGS= V is less than VTP= -2 V, VGS = V ID = 52.5 mA and VGS = V Assumption: IG=IB=0, transistor is saturated (since VDS= VGS) Analysis: Hence saturation assumption is correct. Q-pt: (52.5 mA, V)

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Example The circuit below uses a p-channel enhancement MOSFET with k’(W/L) = 2 mA/V2 and Vt = -1 V. Find the value for R that produces V0 = 10 V.

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**Modifications to Drain Current Equations Channel-Length Modulation**

Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by ΔL). Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L. It can be called; channel length modulation (λ), or Early voltage (VA)

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Example A saturated MOSFET is operated with a constant vGS. The drain current, iD, is found to be 2 mA for vDS = 4 V and 2.2 mA for vDS = 8 V. Find the values of VA, λ and ro.

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Including the effect of Channel Length Modulation in the MOSFET model (Valid in the Saturation region) Output resistance

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**Bias-Point Stability for MOS Amplifiers (source degeneration)**

VGS iD Vt1 Vt2 Variations in K’(W/L) Variation in Vt VG iD RS VGS=VG-iDRS Large Rs stable bias point but requires large supply voltage Rs is called degeneration resistance

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ECE 340 ELECTRONICS I MOS APPLICATIONS AND BIASING.

ECE 340 ELECTRONICS I MOS APPLICATIONS AND BIASING.

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