Presentation on theme: "Goals Investigate circuits that bias transistors into different operating regions. Two Supplies Biasing Four Resistor Biasing Two Resistor Biasing Biasing."— Presentation transcript:
2 GoalsInvestigate circuits that bias transistors into different operating regions.Two Supplies BiasingFour Resistor BiasingTwo Resistor BiasingBiasing using Current MirrorUnderstand Bias Point StabilityInvestigate DC Analysis for P-Channel Transistor
3 Bias Analysis Approach Assume an operation region (generally the saturation region)Use circuit analysis to find VGSUse VGS to calculate ID, and ID to find VDSCheck validity of operation region assumptionsChange assumptions and analyze again if required.NOTE :An enhancement-mode device with VDS = VGS is always in saturation
4 Bias Analysis of n-channel MOSFET Check VGSwe start the analysis by assuming certain operating regionVGS> VtVGS< VTNVDS < VGS –VTNTriode regionVDS > VGS –VTNSat. regionCutoff regioniD=0
5 Example-1Biasing using two voltage supplies for gate and drain terminal
7 Example 2 ( Biasing in Triode Region) AlsoBut VDS<VGS-VTN. Hence, saturation region assumption is incorrect Using triode region equation,Assumption: IG=IB=0, transistor is saturated (since VDS= VGS)Analysis: VGS=VDD=4 Vand ID=1.06 mAVDS<VGS-VTN, transistor is in triode regionQ-pt:(1.06 mA, 2.3 V)
8 Four-Resistor and Two-Resistor Biasing Provide excellent bias for transistors in discrete circuits.Stabilize bias point with respect to device parameter and temperature variations using negative feedback.Use single voltage source to supply both gate-bias voltage and drain current.Generally used to bias transistors in saturation region.Two-resistor biasing uses lesser components that four-resistor biasing and also isolates drain and gate terminals
9 Bias Analysis: Example3 (Four-Resistor Biasing) Assumption: Transistor is saturated, IG=IB=0Analysis: First, simplify circuit, split VDD into two equal-valued sources and apply Thevenin transformation to find VEQ and REQ for gate-bias voltageProblem: Find Q-pt (ID, VDS)Approach: Assume operation region, find Q-point, check to see if result is consistent with operation region
10 Bias Analysis: Example 3 (Four-Resistor Biasing) (contd.) Since VGS<VTN for VGS= V and MOSFET will be cut-off,and ID= 34.4 mAAlso,Since IG=0,VDS>VGS-VTN. Hence saturation region assumption is correct.Q-pt: (34.4 mA, 6.08 V) with VGS= 2.66 V
11 Two Resistor BiasingBiasing the MOSFET using a large drain-to-gate feedback resistance, RG.VDD> Vt MOS is ON and always in saturation(diode connected transistor)
12 Bias Analysis: Example 4 (Two-Resistor Biasing) Since VGS<VTN for VGS= V and MOSFET will be cut-off,Assumption: IG=IB=0, transistor is saturated (since VDS= VGS)Analysis:and ID= 130 mAVDS>VGS-VTN. Hence saturation region assumption is correct.Q-pt: (130 mA, 2.00 V)
13 Additional Biasing Circuits_2 Using constant current source
14 How to implement a current source (Current mirrors) For Q1For Q2
15 N-branch current mirror IrefI1I2InW/L(W/L)1(W/L)2(W/L)n
17 DC –Analysis of P-channel MOS Note: The direction of current is out of the drain for a PMOS
18 Bias Analysis: Example 5 (Two-Resistor biasing for PMOS Transistor) AlsoSince VGS= V is less than VTP= -2 V, VGS = VID = 52.5 mA and VGS = VAssumption: IG=IB=0, transistor is saturated (since VDS= VGS)Analysis:Hence saturation assumption is correct.Q-pt: (52.5 mA, V)
19 ExampleThe circuit below uses a p-channel enhancement MOSFET with k’(W/L) = 2 mA/V2 and Vt = -1 V. Find the value for R that produces V0 = 10 V.
21 Modifications to Drain Current Equations Channel-Length Modulation Increasing vDS beyond vDSsat causes the channel pinch-off point to move slightly away from the drain, thus reducing the effective channel length (by ΔL).Effect of vDS on iD in the saturation region. The MOSFET parameter VA depends on the process technology and, for a given process, is proportional to the channel length L.It can be called; channel length modulation (λ), or Early voltage (VA)
22 ExampleA saturated MOSFET is operated with a constant vGS. The drain current, iD, is found to be 2 mA for vDS = 4 V and 2.2 mA for vDS = 8 V. Find the values of VA, λ and ro.
24 Including the effect of Channel Length Modulation in the MOSFET model (Valid in the Saturation region)Output resistance
25 Bias-Point Stability for MOS Amplifiers (source degeneration) VGSiDVt1Vt2Variations in K’(W/L)Variation in VtVGiDRSVGS=VG-iDRSLarge Rs stable bias point but requires large supply voltageRs is called degeneration resistance
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