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Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Topics n Electrical properties of static combinational gates: –transfer characteristics; –delay;

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Presentation on theme: "Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Topics n Electrical properties of static combinational gates: –transfer characteristics; –delay;"— Presentation transcript:

1 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Topics n Electrical properties of static combinational gates: –transfer characteristics; –delay; –power. n Effects of parasitics on gate. n Driving large loads.

2 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Logic levels n Solid logic 0/1 defined by V SS /V DD. n Inner bounds of logic values V L /V H are not directly determined by circuit properties, as in some other logic families. logic 1 logic 0 unknown V DD V SS VHVH VLVL

3 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Logic level matching n Levels at output of one gate must be sufficient to drive next gate.

4 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Transfer characteristics n Transfer curve shows static input/output relationshiphold input voltage, measure output voltage.

5 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Inverter transfer curve

6 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Logic thresholds n Choose threshold voltages at points where slope of transfer curve = -1. n Inverter has a high gain between V IL and V IH points, low gain at outer regions of transfer curve. n Note that logic 0 and 1 regions are not equal sizedin this case, high pullup resistance leads to smaller logic 1 range.

7 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Noise margin n Noise margin = voltage difference between output of one gate and input of next. Noise must exceed noise margin to make second gate produce wrong output. In static gates, t= voltages are V DD and V SS, so noise margins are V DD -V IH and V IL - V SS.

8 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Delay n Assume ideal input (step), RC load.

9 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Delay assumptions n Assume that only one transistor is on at a time. This gives two cases: –rise time, pullup on; –fall time, pullup off. n Assume resistor model for transistor. Ignores saturation region and mischaracterizes linear region, but results are acceptable.

10 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Current through transistor n Transistor starts in saturation region, then moves to linear region.

11 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Capacitive load n Most capacitance comes from the next gate. n Load is measured or analyzed by Spice. n C l : load presented by one minimum-size transistor. C L = (W/L) i C l

12 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Resistive model for transistor n Average V/I at two voltages: –maximum output voltage –middle of linear region n Voltage is V ds, current is given I d at that drain voltage. Step input means that V gs = V DD always.

13 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Resistive approximation

14 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Ways of measuring gate delay n Delay: time required for gates output to reach 50% of final value. n Transition time: time required for gates output to reach 10% (logic 0) or 90% (logic 1) of final value.

15 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Inverter delay circuit n Load is resistor + capacitor, driver is resistor.

16 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Inverter delay with model model: gate delay based on RC time constant. n V out (t) = V DD exp{-t/(R n +R L )/ C L} n t f = 2.2 R C L n For pullup time, use pullup resistance.

17 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf model inverter delay n 0.5 micron process: –R n = 6.47 k –C l = 0.89 fF –C L = 1.78 fF n So –t d = 0.69 x 6.47E3 x 1.78E-15 = 7.8 ps. –t f = 2.2 x 6.47E3 x 1.78E-15 = 26.4 ps.

18 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Quality of RC approximation

19 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Quality of step input approximation

20 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Power consumption analysis n Almost all power consumption comes from switching behavior. n Static power dissipation comes from leakage currents. n Surprising result: power consumption is independent of the sizes of the pullups and pulldowns.

21 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Other models n Current source model (used in power/delay studies): –t f = C L (V DD -V SS )/I d – = C L (V DD -V SS )/0.5 k (W/L) (V DD -V SS -V t ) 2 n Fitted model: fit curve to measured circuit characteristics.

22 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Body effect and gates n Difference between source and substrate voltages causes body effect. n Source for gates in middle of network may not equal substrate: 0 0 Source above VSS

23 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Body effect and gate input ordering n To minimize body effect, put early arriving signals at transistors closest to power supply: Early arriving signal

24 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Power consumption circuit n Input is square wave.

25 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Power consumption n A single cycle requires one charge and one discharge of capacitor: E = C L (V DD - V SS ) 2. n Clock frequency f = 1/t. n Energy E = C L (V DD - V SS ) 2. n Power = E x f = f C L (V DD - V SS ) 2.

26 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Observations on power consumption n Resistance of pullup/pulldown drops out of energy calculation. n Power consumption depends on operating frequency. –Slower-running circuits use less power (but not less energy to perform the same computation).

27 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Speed-power product n Also known as power-delay product. n Helps measure quality of a logic family. n For static CMOS: –SP = P/f = CV 2. n Static CMOS speed-power product is independent of operating frequency. –Voltage scaling depends on this fact.

28 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Parasitics and performance b a c

29 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Effect of parasitics n a: Capacitance on power supply is not bad, can be good in absence of inductance. Resistance slows down static gates, may cause pseudo-nMOS circuits to fail.

30 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Effects of parasitics, contd n b: Increasing capacitance/resistance reduces input slope. n c: Similar to parasitics at b, but resistance near source is more damaging, since it must charge more capacitance.

31 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Driving large loads n Sometimes, large loads must be driven: –off-chip; –long wires on-chip. n Sizing up the driver transistors only pushes back the problemdriver now presents larger capacitance to earlier stage.

32 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Cascaded driver circuit

33 Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf Optimal sizing n Use a chain of inverters, each stage has transistors a larger than previous stage. n Minimize total delay through driver chain: –t tot = n(C big /C g ) 1/n t min. n Optimal number of stages: –n opt = ln(C big /C g ). Driver sizes are exponentially tapered with size ratio.


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