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ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 11 Ch 11 Bipolar Transistors and Digital Circuits *Examine bipolar junction transistor (BJT) use in inverters.

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Presentation on theme: "ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 11 Ch 11 Bipolar Transistors and Digital Circuits *Examine bipolar junction transistor (BJT) use in inverters."— Presentation transcript:

1 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 11 Ch 11 Bipolar Transistors and Digital Circuits *Examine bipolar junction transistor (BJT) use in inverters for logic circuits. *Basic Inverter (RTL) à One npn transistor and a load resistor *BJT Inverters à Transistor-Transistor Logic (TTL) à Emitter-Coupled Logic (ECL) *Analyze to understand inverter performance: à voltage transfer characteristic, à noise margins, à fan-in and fan-out limits, à power dissipation and à switching speed. 2-input ECL OR / NOR Gate Y = A+B AB VRVR

2 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 12 Bipolar Transistor Operation *Transistor regions of operation à Forward Active ®V BE > 0 E jnc forward ®V BC < 0 C jnc reverse à Cutoff ®V BE < 0 E jnc reverse ®V BC < 0 C jnc reverse à Saturation ®V BE > 0 E jnc forward ®V BC > 0 C jnc forward n n p Emitter Collector Base C E B V BE V BC V CE + + +_ _ _ Cutoff I C ≈ 0 Active I c = βI b Saturation I C < β I B Note: V CE = V BE +V CB = V BE - V BC ICIC V CE

3 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 13 Bipolar Transistor Operation Saturation I C < β I B Cutoff I C ≈0 Active I c = βI b ICIC V CE *Forward Active *Electron injection at emitter and collection at collector ®V BE > 0 E jnc forward ®V BC < 0 C jnc reverse ®I c = β I b * Cutoff * No electron injection at Emitter ®V BE < 0 E jnc reverse ®V BC < 0 C jnc reverse ®I C ≈ 0 * Saturation * Electron injection from both E & C ®V BE > 0 E jnc forward ®V BC > 0 C jnc forward ®I C < β I B Transistor regions of operation

4 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 14 Bipolar Transistor Operation - DC *Base bias V BE determines I B *V CC with R C determine output load line. *Base I B with output load line determines Quiescent Point (V CE, I C ) IBIB V BE Base Load Line Output Load Line ICIC V CE Quiescent Point ICIC V CE V BE IBIB DC Base Current

5 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 15 Bipolar Transistor Operation – Small Signal AC *In small signal amplifiers, à AC signal at input is small –> base current variation is small. à Device moves around DC quiescent point à Device stays in the active region à Amplifier produces current and voltage gain depending upon the configuration, e.g. common emitter (above). iBiB iCiC v BE v CE V BB +v i

6 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 16 Bipolar Transistor Operation – Digital Circuits *Input signal v i is large. à V BE and I B changes are large. à Important applications  digital circuits and power amplifiers à Device can be in active, saturation or cutoff depending on V BE and I B. *Transistor still operates on the load line. à Moves from cutoff thru active to saturation or vice versa as the input signal changes. ICIC V CE Cutoff I C ≈ 0 Active I c =βI b Saturation I C < β I B

7 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 17 Bipolar Transistor Operation - Characteristics *Each region of device operation has its own unique characteristics *Active à Current gain I c = β I b à V BE = V BE,active ≈ 0.7 V (typical value) à V CE,active ≈ ?, NO typical value! *Saturation à Reduced current gain I C < β I B à V BE = V BE, sat ≈ 0.8 V (typical value) à V CE = V CE, sat ≈ 0.2V (typical value) *Cutoff à No current gain I C ≈ 0, I B ≈ 0 à V BE < O à V CE,cutoff ≈ ?, NO typical value! Cutoff I C  0 Active I c = βI b ICIC V CE Saturation I C < β I B IBIB V BE 0.7 V 0.8V ~ 0.2 V

8 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 18 Resistor Transistor Logic (RTL) *RTL Logic à Earliest and simplest logic à “0” = low voltage à “1” = high voltage *Inverter is the basic building bock *Combine two inputs in parallel to implement NOR *Combine two inputs in series to implement NAND *Transistors operate in cutoff for low “0” input (base) voltage, so I C ≈ 0 and output is high “1”. *Transistors operate in saturation for high “1” input (base) voltage, so I C ~ mA’s and the output is low “0” due to IR drop across R C. vivi vovo vivi vovo

9 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 19 Basic Bipolar Transistor Inverter (RTL) *Resistor Transistor Logic (RTL) *For low v i input, output v o is high à Transistor is off (cutoff) since i B ≈ 0 because base-emitter junction is not biased sufficiently (V BE is too small). à Since i B ≈ 0, then i C ≈ 0 because i C ≈ β i B. à So v o = V CC - i C R C ≈ V CC *For high v i input, output v o is low à Transistor is on since i B > 0 because base-emitter junction is biased sufficiently (V BE is large). à Since V BE is large (~0.8 V), i B >> 0, then i C >> 0 since i C ≈ β i B. à So v o = V CC - i C R C is very small. à Transistor driven into saturation region so. v o = V CE,sat ≈ 0.2V V BE + n n p ICIC Cutoff I C ≈ 0 Active I c =βI b Saturation I C < β I B ICIC V CE ~ 0.2 V IBIB V BE 0.7 V 0.8V

10 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 110 Basic Bipolar Transistor Inverter (RTL) *Transistor operates along load line. *Transistor operates in cutoff when input is low since i B ≈ 0. *As input v i increases, i B increases and transistor moves into active region. *As input v i increases further, transistor moves into saturation region and V CE goes towards zero. V CE + V BE + cutoff active Saturation i C /i B < β 0 Input low v i small Input high v i large ICIC V CE ICIC Output Load Line

11 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 111 RTL Voltage Transfer Characteristic *Region I (A to B) à Transistor is in cutoff à V BE is small, i B ≈ 0, v o = V CC. *Region II (B to C) à Transistor is on in the active mode (i C = β i B ). à i B and V BE are larger; V BE ≈ 0.7V à i C and i B increase as v i and V BE increase. à v o and V CE falls as i c R C increases. *Region III (C to D) à Transistor is in the saturation mode (i C < β i B ). à i B and V BE are larger, V BE ≈ 0.8 V à i C is larger à V CE is small, ≈ V CE,sat ≈ 0.2V V CE + V BE + D A III III V BE IBIB vivi vovo V CC = 5 V C B

12 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 112 Noise Margins *Noise margins are a measure of the reliability of the technology. *Measure of the sensitivity to noise. *Consider one inverter driving an identical inverter. *How large a noise spike can be tolerated before an error occurs? Drive Inverter Load Inverter Load Inverter Drive Inverter For output of driver high (v 01 =V OH ), then input of load inverter is high (v i2 =V OH ). A negative noise spike on input of load inverter reduces input signal. Trouble when net input signal is less than V IH so noise margin is NM H = V OH - V IH. Similarly, for the low state NM L = V IL - V OL. v 01 v 02 v i2 v i1 NM H NM L v i1 v 01 v i2 v 02 V IH V IL V OL V OH

13 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 113 RTL Inverter Noise Margins *Noise Margin for Low State à NM L = V IL - V OL à V IL = V BE,active = 0.7 V à V OL = V CE,sat = 0.2 V à NM L = V IL - V OL = 0.7 V V = 0.5 V *Noise Margin for High State à NM H = V OH - V IH à V OH = V CC = 5 V à V IH = V BE,sat = 0.8 V à NM H = V OH - V IH = 5 V V = 4.2 V *Unequal noise margins for high and low states. V CE + V BE + D A III III V BE IBIB vivi vovo V OH V OL V IH V IL V CC = 5 V V OL V OH NM H NM L C B

14 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 114 RTL Power Dissipation *Output High State (Low input) à Transistor is in cutoff so i C  0. à No static power dissipation for high state, P H = 0. *Output Low State (High input) à Transistor is in saturation so v o = V CE,sat = 0.2 V. à i C = (V CC - V CE,sat )/R C = (5V V)/10K = 0.48 mA. à P L =V CC i C = (5 V)(0.48 mA) = 2.4 mW à Average P = 1/2(P H + P L ) = 1.2 mW V CE + V BE + DC BA III III V BE IBIB vivi vovo V OH V OL V IH V IL R C = 10K V CC = 5 V

15 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 115 RTL Propagation Delay *Output going high à Transistor turned off (cutoff) à Charging current flows through R C à t PLH is time it takes the output to rise from V OL = V CE,sat = 0.2 V to 1/2(V OH + V OL ) = 2.6 V V CE + V BE + D A III III vivi vovo V OH V OL V IH V IL C vovo + i Cap iRiR t vovo V CC V CE,sat V CC = 5 V t PLH Long charge – up time! C B

16 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 116 RTL Propagation Delay *Output going high à Transistor turned off (cutoff) (M  N) à Charging current flows through R C à t PLH is time it takes the output to rise from V OL = V CE,sat = 0.2 V to 1/2(V OH + V OL ) = 2.6 V (N  O) V CE + V BE + DC BA III III vivi vovo V OH V OL V IH V IL C vovo + i Cap iRiR t vovo V CC V CE,sat V CC =5V t PLH P Transient Response M  N  O M N O ICIC V CE

17 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 117 RTL Propagation Delay *Output going low à Transistor turned on (saturation) and providing discharge current (P  R) à But current also flows through R C à t PHL is time it takes the output to fall from V OH = V CC = 5 V to 1/2(V OH + V OL ) = 2.6 V (R  S) V CE + V BE + DC BA III III vivi vovo V OH V OL V IH V IL C vovo + i Cap iRiR t vovo V CC V CE,sat P R S V CC = 5 V t PHL Transient Response P  R  S ICIC V CE

18 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 118 RTL Propagation Delay *Output going low V CE + V BE + C vovo + i Cap iRiR P R S V CC = 5 V ICIC V CE Short discharge time!

19 ECES 352 Winter 2007Ch 11 Bipolar Digital Pt. 119 Resistor Transistor Logic (RTL) *RTL provides simple, basic digital technology based on bipolar transistors and resistors. Logic levels and noise margins à Noise Margin for Low State ®NM L = V IL – V O = 0.7 V V = 0.5 V à Noise Margin for High State ®NM H = V OH - V IH = 5 V V = 4.2 V à Unequal noise margins for high and low states. *Propagation delays à Output going low à Output going high à Propagation delay *Power – Delay Product vivi vovo vivi vovo


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