1. ECE 511: Digital System & Microprocessor

2. Course Outline WeekSubject W1-W2Digital Logic Review W2-W3Microprocessor Architecture & Overview W3-W6Microprocessor Instruction Set & Programming W6-W9Memory Interfacing W10-W14Parallel I/O Interfacing

3. References J. L. Antonakos, “The 68000 Microprocessor: Hardware and Software Principles & Applications,” 5 th Ed., Pearson Prentice-Hall, 2004. C. M. Gilmore, “Microprocessors: Principles & Applications,” 2 nd Ed., McGraw-Hill, 1995. A. Clements, “Microprocessor System Design,” PWS- Kent, 1992. J. Palmer & D. Perlman, “Introduction to Digital Systems,” Schaum’s Outlines Series, McGraw-Hill, 1993.

4. Course Evaluation Tests x 230% Quizzes x 320% Mini Projects50%

5. If you have problems, please contact me: Ahmad Ihsan bin Mohd Yassin Rm. T2-A13-1A, Dept. of Comp. Eng. Faculty of Elect. Eng. UiTM, Shah Alam. 03-55436118, 017-2576295 *Please call before you see me.

6. Digital Logic Review: Part I ECE 511: Digital System & Microprocessor.

7. What we will learn in this session: Review of logic gates. Flip-flops. Universal representation of logic gates. Decoders.

8. Gates

9. What are gates? Gates are:  Simple electronic devices.  Constructed using transistors.  Used to design digital systems. Three basic gates:  AND  OR  NOT Usually packed into ICs.

10. Gates as Building Blocks

11. Basic Gate - AND The AND gate is similar to multiply operation. A AND B C A BC 0 1 0 1 0 0 1 1 0 0 0 1 TRUTH TABLE

12. Basic Gate - OR The OR gate is similar to add operation. OR A B C A BC 0 1 0 1 0 0 1 1 0 1 1 1 TRUTH TABLE

13. Basic Gate - NOT The NOT gate performs the inverse operation. NOT A B TRUTH TABLE A B 0 1 1 0

14. Extended Gates Combination of basic gates to perform complex functions:  NAND  NOR  XOR  XNOR  Flip-Flops

15. NAND Gate Adds NOT after AND gate. AND outputs are inverted  NAND (NOT-AND). A AND B C NOT A NAND B C A BC 0 1 0 1 0 0 1 1 1 1 1 0 TRUTH TABLE

16. NOR Gate Adds NOT after OR gate. OR outputs are inverted  NOR (NOT-OR). OR A B C NOT C NOR A B A BC 0 1 0 1 0 0 1 1 1 0 0 0 TRUTH TABLE

17. XOR Gate XOR performs the Exclusive Or operation. When A=B, C=0; when A≠B, C=1. A BC 0 1 0 1 0 0 1 1 0 1 1 0 TRUTH TABLE XOR A B C

18. XNOR Gate Adds NOT after XOR gate. XOR outputs inverted  XNOR (NOT XOR). A BC 0 1 0 1 0 0 1 1 1 0 0 1 TRUTH TABLE XOR A B C NOTXOR A B C

19. Flip-Flops

20. Extended gate. 2 gates, feedback connections. 2 inputs, 4 states. Used as memory:  Each FF stores 1 bit.  Unchanged at “keep” state. More complex ones may:  Use timing from CLK.  Perform bit toggle.

21. RS Flip-Flop 4 states:  Three stable.  One not stable. 2 inputs, 2 outputs. May contain clock (CLK) signal.

22. RSFF - NOR Implementation *Assuming initial condition: S = 0, R = 0, Q = 0 Q prev SRQ N/A000 0101 1010 Doesn’t matter 11N/A Unstable Output unchanged Output set (Q = 1) Output reset (Q = 0) Q’ 1 0 1 N/A *As long as S=0 and R=0, Q will always remain at previous state. S R Q’ Q

23. RS Flip-Flop (NAND Implementation) *Assuming initial condition: S = 0, R = 0, Q = 0 Q prev SRQ N/A000 0101 1010 Doesn’t matter 11N/A Unstable Output unchanged Output set (Q = 1) Output reset (Q = 0) Q’ 1 0 1 N/A *As long as S=0 and R=0, Q will always remain at Q prev. S R Q Q’

24. Clocked RS S R Q’ Q CLK Q prev SRQ N/A000 0101 1010 Doesn’t matter 11N/A Unstable Output unchanged Output set (Q = 1) Output reset (Q = 0) Q’ 1 0 1 N/A CLK ↑ ↑ ↑ Doesn’t matter Only active when CLK is ↑ Reduced sensitivity to noise.

25. JK Flip-Flop Same as RS, but forbidden state used to toggle bit. Can also be clocked using CLK. Q prev SRQ N/A000 0101 1010 Q 11Q Toggle Output unchanged Output set (Q = 1) Output reset (Q = 0) Q’ 1 0 1 Q

26. JK Flip-Flop (Palmer & Perlman, pg. 200) Q prev SRQ N/A000 0101 1010 Q 11Q Toggle Output unchanged Output set (Q = 1) Output reset (Q = 0) Q’ 1 0 1 Q J K Q Q

27. Clocked JK (Palmer & Perlman, pg. 200) Q prev SRQ N/A000 0101 1010 Q 11Q Toggle Output unchanged Output set (Q = 1) Output reset (Q = 0) CLK ↑ ↑ ↑ ↑ J K Q Q

28. D-Flip-Flop Data latch. Modification of RSFF. Stores 1-bit of information.  Can be combined to store more. How data stored in memory.

29. D-Flip-Flop D Q’ Q EN Q prev DQ Doesn’t Matter 11 00 Output set (Q = 1) Output reset (Q = 0) Q’ 0 1 EN 1 1 Only active when EN is 1

30. D-Flip-Flop: Timing Diagram D EN Q

31. Storing 8-bits using DFF DFF Q3Q5Q6Q7Q1Q2Q4Q0 EN D3D5D6D7D1D2D4D0

32. Asynchronous Latch Allows both synchronous & asynchronous operations:  Synchronous: CLK driven (Clocked JK).  Asynchronous: similar to RSFF. 5 inputs, 2 outputs:  J, K and CLK for synch. operation.  PR, CLR for asynch. operation.

33. Asynchronous Latch (Perlman, pg. 201) CLK J K Q Q CLR PRE CLRQ 11Follows J, K, CLK (Synch. JK) 10Q = 0, resets output. 01Q = 1, sets output. 00Not valid. PRECLRQ 00Follows J, K, CLK (Synch. JK) 01Q = 0, resets output. 10Q = 1, sets output. 11Not valid. CLK J K Q Q CLR PRE

34. Universal Gates – NAND and NOR

35. NAND and NOR as Universal Gates In industry, NAND and NOR gates are most common. Reason?  Can be used to represent any gate (functionally complete).  Easiest & cheapest to produce.

36. NAND Logic

37. NOR Logic

38. NAND Logic

39. NOR Logic

40. IC 4011 IC 7402

41. Decoders

42. Electronic device that:  Reverse of an encoder.  “Translates” binary codes back into signal.  Converts n inputs into 2 n combinations. Uses:  Activate devices for use by µP.  Memory, I/O interfacing.

43. Encoder vs. Decoder 8  3 Encoder I0I0 I7I7 I6I6 I5I5 I4I4 I3I3 I2I2 I1I1 Y2Y2 Y0Y0 Y1Y1

44. Encoder vs. Decoder 3  8 Decoder I0I0 I7I7 I6I6 I5I5 I4I4 I3I3 I2I2 I1I1 Y2Y2 Y0Y0 Y1Y1 Y2Y2 Y1Y1 Y0Y0 11 000 100 001 101 100 11 0 111 0 I4I4 I5I5 I6I6 I7I7 I0I0 I1I1 I2I2 I3I3 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0

45. What Goes on Inside a Decoder? Y0 Y1 Y2 I 0 = Y 0 Y 1 Y 2 I 2 = Y 0 Y 1 Y 2 I 3 = Y 0 Y 1 Y 2 I 4 = Y 0 Y 1 Y 2 I 5 = Y 0 Y 1 Y 2 I 6 = Y 0 Y 1 Y 2 I 7 = Y 0 Y 1 Y 2 I 1 = Y 0 Y 1 Y 2

46. Decoders in Action Decoder Device Code CodeDevice 000LED 001DC Motor 010Memory #1 110LCD Display 011Memory #2 100Memory #3 101Memory #4 Activate Signal

47. 74LS139 Dual 2-4 Line Decoder Motorola 2-4 decoder. 2 x decoders in one IC. 16 pins total:  2 inputs, 4 outputs (active low).  Vcc (±5V) and GND.  2 x Enable pins.

48. 74LS139 Dual 2-4 Line Decoder EaEa A 0a A 1a O 0a O 1a O 2a O 3a EbEb A 0b A 1b O 0b O 1b O 2b O 3b

49. 74LS139 Truth Table EI0I0 I1I1 O3O3 O0O0 O1O1 O2O2 1XX1111 0001011 0101101 0011110 0110111

50. 74LS138 3-8 Line Decoder Motorola 3-8 decoder. 1 x decoder in one IC. 16 pins total:  3 inputs, 8 outputs (active low).  Vcc (±5V) and GND.  3 x Enable pins.

51. 74LS138 3-8 Line Decoder E1E1 A0A0 A1A1 O0O0 O1O1 O2O2 O3O3 O4O4 O5O5 O6O6 O7O7 E2E2 E3E3 A2A2

52. E1E1 I0I0 I1I1 O3O3 O0O0 O1O1 O2O2 1XX1111 XXX1111 XXX1111 0001011 0101101 E2E2 X 1 X 0 0 E3E3 X X 0 1 1 I2I2 X X X 0 0 O7O7 O4O4 O5O5 O6O6 1111 1111 1111 1111 1111 00111100101111 01101110101111 0001111 0101111 0 0 1 1 1 1 1011 1101 00111110111110 01111110110111 74LS138 Truth Table

53. Conclusion Gates: most basic elements in circuits.  Can be extended to perform advanced functions.  Some types are universal.  Flip-flops can store data – feedback. Decoders transform code into original signals.  Can be used to control access to hardware.

54. The End Please read: Palmer & Perlman, pg.194-203. http://computerscience.jbpub.com/ecoa/2e/Null03.pdf