# + CS 325: CS Hardware and Software Organization and Architecture Sequential Circuits 1.

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+ CS 325: CS Hardware and Software Organization and Architecture Sequential Circuits 1

+ Outline Sequential Circuits Overview Clock Signals Classification of Sequential Circuits Latches/Flip Flops S-R Latch S-R Flip Flop D Flip Flop J-K Flip Flop

+ Sequential Circuits Unlike Combinational Circuits, Sequential Circuits have some form of inherent “Memory” as they are able to take into account their previous input state, as well as their current input state. Output of Sequential Circuits based on three states: Present input state Previous input state And/Or previous output state

+ Sequential Circuits Sequential Circuits stay fixed in their current state until the next clock cycle signal changes in one of the states.

+ Clock Signals Clock: A circuit that emits a series of pulses with precise pulse width (how long the pulse lasts) and interval (how long until the next pulse). Number of pulses per second is the Clock Frequency, commonly between 1 and 4 billion pulses per second (1 – 4 GHz). Clock frequency is controlled by a crystal oscillator. Time between edges of 2 consecutive pulses is the clock cycle time. Clock frequency = 1 / clock cycle time

+ Sequential Circuit Representation

+ Sequential Circuits “Sequential” means actions occur one after the other. In sequential circuits, the clock signal determines when actions occur. In the same way that gates are the building blocks of combinational circuits, latches and flip-flops are the building blocks of sequential circuits. Latches and flip-flops are circuit elements whose output depends on current inputs and previous input and output states.

+ Classification of Sequential Circuits

+ Event Driven: Asynchronous circuits that change state immediately when enabled. Ex: Latch Clock Driven: Synchronous circuits that are synchronized to a specific clock signal. EX: Flip-Flop Pulse Driven: Combination of Event and Clock driven sequential circuits that responds to triggering pulses.

+ Latches/Flip-Flops

+ S–R Latch Level triggered, asynchronous Two inputs: Set, Reset Has feedback so output Q not determined by just the 2 inputs. Two stable states for R = S = 0. 0 or 1 depending on Q

+ S–R Latch Two stable states: S momentarily set to 1 R momentarily set to 1 Q = 1 Q = 0

+ S–R Latch Memory Q is the value of the bit. Setting S = 1 (R remains 0) sets the value of Q to 1. State is stable even if S is returned to 0. Setting R = 1 (S remains 0) sets the value of Q to 0. State is stable even if R is returned to 0. State Q = 1 State Q = 0

+ S–R Latch Definition State Table Simplified State Table Current Inputs Current State Next State SRQnQn Q n+1 0000 0011 0100 0110 1001 1011 110X 111X SR 00QnQn 010 101 11X

+ Clocked S-R Latch (S-R Flip-Flop) Synchronous sequential circuit Based on clock pulse Events in a computer are typically synchronized to a clock pulse, so that changes occur only when a clock pulse changes state.

+ Clocked S-R Flip-Flop Current InputsCurrent State Next State CLKSRQnQn Q n+1 00000 10000 00011 10010 00100 10100 00111 10110 01000 11001 01011 11011 0110X 1110X 0111X 1111X

+ S-R Flip-Flop Block Diagram

+ D Flip-Flop

+ DQ n+1 00 11

+ D Flip-Flop Block Diagram

+ D Flip-Flop Uses

+ J-K Flip-Flop Synchronous sequential circuit Based on clock pulse The J-K Flip Flop is the most widely used of all flip-flop designs. The sequential operation is exactly the same as for the S-R Flip Flop. The difference is the J-K Flip Flop has no invalid or forbidden input states. JKQ n+1 00Qn 010 101 11

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