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Sequential logic circuits. 2 Outline Sequential Circuit Models –Asynchronous –Synchronous Latches Flip-Flops.

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Presentation on theme: "Sequential logic circuits. 2 Outline Sequential Circuit Models –Asynchronous –Synchronous Latches Flip-Flops."— Presentation transcript:

1 Sequential logic circuits

2 2 Outline Sequential Circuit Models –Asynchronous –Synchronous Latches Flip-Flops

3 3 Sequential logic circuits The main characteristic of combinational logic circuits is that their output values depend on their present input values. Sequential logic circuits differ from combinational logic circuits because they contain memory elements so that their output values depend on both present and past input values

4 4 Sequential logic circuits Sequential circuits can be Asynchronous or synchronous. Asynchronous sequential circuits change their states and output values whenever a change in input values occurs. Synchronous sequential circuits change their states and output values at fixed points of time, i.e. clock signals.

5 5 Sequential Circuit Models Universal model

6 6 Memory Devices Latches A latch is a memory element whose excitation signals control the state of the device. A latch has two stages set and reset. Set stage sets the output to 1. Reset stage set the output to 0. Flip-flops A flip-flop is a memory device that has clock signals control the state of the device.

7 7 LatchFlip-flop

8 8 Latches RS Latch The RS latch is the basic memory element consists of two cross-coupled NOR gates. It has two input signals, S set signal and R reset signal. It also has two outputs Q and Q'; and two states, a set state when Q = 1 and a reset state when Q = 0 (Q' = 1)

9 9 SRQQ' SRQ 00 hold 01 0 reset 10 1 set 11 unstable

10 10 RS Latch excitation table SRQ(t)Q(t)Q(t+1) 0000 Hold Reset Q(t+1) = S(t) + R'(t)Q(t) Set Q + = S+ R'Q X Forbidden 111X

11 11 SRQQ' SRQ 00 unstable 01 0 reset 10 1 set 11 hold

12 12 Timing Diagram of RS-Latch

13 13 JK Latch SRQ(t)Q(t)Q(t+1) 0000 Hold Reset Set Q + = K'Q+ JQ' toggle 1110

14 14 Level-Sensitive Latches A level-sensitive latch is a latch with an additional enable input. RS latch

15 15 RS Latch with Enable CSRQ(t)Q(t)Q(t+1) 0XX00 Hold 0XC Reset Set toggle 11110

16 16 D Latch CDQ(t)Q(t)Q(t+1) 0X00 Hold 0X Reset Set 1111 Q + = D

17 17 Flip-Flops A flip-flop is a level-sensitive latch with a clock input. RS flip-flop Q + = S +R'Q


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