# Sequential logic circuits. 2 Outline Sequential Circuit Models –Asynchronous –Synchronous Latches Flip-Flops.

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Sequential logic circuits

2 Outline Sequential Circuit Models –Asynchronous –Synchronous Latches Flip-Flops

3 Sequential logic circuits The main characteristic of combinational logic circuits is that their output values depend on their present input values. Sequential logic circuits differ from combinational logic circuits because they contain memory elements so that their output values depend on both present and past input values

4 Sequential logic circuits Sequential circuits can be Asynchronous or synchronous. Asynchronous sequential circuits change their states and output values whenever a change in input values occurs. Synchronous sequential circuits change their states and output values at fixed points of time, i.e. clock signals.

5 Sequential Circuit Models Universal model

6 Memory Devices Latches A latch is a memory element whose excitation signals control the state of the device. A latch has two stages set and reset. Set stage sets the output to 1. Reset stage set the output to 0. Flip-flops A flip-flop is a memory device that has clock signals control the state of the device.

7 LatchFlip-flop

8 Latches RS Latch The RS latch is the basic memory element consists of two cross-coupled NOR gates. It has two input signals, S set signal and R reset signal. It also has two outputs Q and Q'; and two states, a set state when Q = 1 and a reset state when Q = 0 (Q' = 1)

9 SRQQ' 1010 0010 0101 0001 1100 SRQ 00 hold 01 0 reset 10 1 set 11 unstable

10 RS Latch excitation table SRQ(t)Q(t)Q(t+1) 0000 Hold 0011 0100 Reset Q(t+1) = S(t) + R'(t)Q(t) 0110 1001 Set Q + = S+ R'Q 1011 110X Forbidden 111X

11 SRQQ' 1010 1110 0101 1101 0011 SRQ 00 unstable 01 0 reset 10 1 set 11 hold

12 Timing Diagram of RS-Latch

13 JK Latch SRQ(t)Q(t)Q(t+1) 0000 Hold 0011 0100 Reset 0110 1001 Set Q + = K'Q+ JQ' 1011 1101 toggle 1110

14 Level-Sensitive Latches A level-sensitive latch is a latch with an additional enable input. RS latch

15 RS Latch with Enable CSRQ(t)Q(t)Q(t+1) 0XX00 Hold 0XC11 10000 10011 10100 Reset 10110 11001 Set 11011 11101 toggle 11110

16 D Latch CDQ(t)Q(t)Q(t+1) 0X00 Hold 0X11 1000 Reset 1010 1101 Set 1111 Q + = D

17 Flip-Flops A flip-flop is a level-sensitive latch with a clock input. RS flip-flop Q + = S +R'Q

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