# 1 Sequential Ckts, Latches and Timing Issues Today: Sequential Circuits, LatchesFirst Hour: Sequential Circuits, Latches –Section 6.1.1 of Katz’s Textbook.

## Presentation on theme: "1 Sequential Ckts, Latches and Timing Issues Today: Sequential Circuits, LatchesFirst Hour: Sequential Circuits, Latches –Section 6.1.1 of Katz’s Textbook."— Presentation transcript:

1 Sequential Ckts, Latches and Timing Issues Today: Sequential Circuits, LatchesFirst Hour: Sequential Circuits, Latches –Section 6.1.1 of Katz’s Textbook –In-class Activity #1 Second Hour: J-K latch, Timing issues Section 6.1.2-6.1.4 of Katz’s Textbook –In-class Activity #2

2 Combinational vs Sequential Logic Combinational logic circuits Circuits whose outputs are a function of their current inputs only Sequential logic circuits AND Circuits whose outputs are a function of their current inputs AND stored information about previous inputs Contain storage elements Contain feedback connections

3 Block diagram of a sequential network Sequential Switching Networks INPUTS OUTPUTS CURRENT STATE NEXT STATE Combinational network Storage elements

4 Propagation Delay Let’s consider a buffer that has a propagation delay of t pd Suppose the input of the buffer is set to Y. After t pd seconds the output will be Y. Y t pd Y

5 Feedback YY If the input of the buffer is Y for at least t pd seconds, after t pd seconds the output becomes Y. a storage elemen t ! Suppose we connect the output to its own input Now, suppose we connect the output to its own input. Then this process is repeated indefinitely. It is independent of the value of Y !

6 Storage Elements t pd Buffers are usually implemented using a pair of inverters t pd 1212 1212

7 Storage Elements Solution!! Replace the inverters with NOR gates R S X Y t pd 1212 1212 Problem!! Problem!! No way to change the information

8 The R-S Latch R S Q Q R-S Latch R S X Y Q Q Since X and Y are always complements, we rename them Q and Q Redrawn to show symmetry

9 R-S Latch Walk-thru R=0 S=0 Q Q R=0 => invert Q S=0 => invert Q Result: Hold on to Q

10 R-S Latch Walk-thru R=1 S=0 Q=0 Q = 1 R=1 => Q = 0 (“reset function”) S=0 => invert Q Result: Reset Q to 0

11 R-S Latch Walk-thru R=0 S=1 Q=1 Q = 0 S=1 => set to 0 Result: “set” Q to 1 R=0 => invert Q Q

12 R-S Latch Walk-thru R=1 S=1 Q Q R=1 => try to set Q to 0! S=1 => try to set to 0! Result: unstable race condition ! Q

13 Cross-Coupled NOR Gates This is the basis of current memory chips SRQ 00 Q hold 010 reset 101 set 11 unstable avoid Functional truth table This device is called a latch

14 Timing Diagram Cross-Coupled NOR Gates Timing Waveform Reset Hold Set Forbidden State ResetSet Forbidden State Race R S Q \Q

15 Do Activity #1 Now Cross-Coupled NOR Gates: R-S Latch Timing Waveform Reset Hold Set Forbidden State ResetSet Forbidden State Race R S Q \Q SRQ 00 Q hold 010 reset 101 set 11 unstable avoid Functional truth table

16 The R-S Latch Next State Table S R Q Q + 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 NOT 1 1 1 ALLOWED Q + is the next state: the state after input changes propagate to the outputs Q + is the next state: the state after input changes propagate to the outputs ?? XX What is the next state for these inputs? Use Don’t-Care for outputs of forbidden inputs

17 The R-S Latch Next State Table S R Q Q + 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 XNOT 1 1 1 XALLOWED Functional behavior label HOLD RESET SET

18 R-S Latch Characteristic Equation Q SR 00 01 11 10 000X1 110X1 S R Q Q + 0 0 0 0HOLD 0 0 1 1 0 1 0 0RESET 0 1 1 0 1 0 0 1SET 1 0 1 1 1 1 0 XNOT 1 1 1 XALLOWED K-map for Q + Characteristic equation Q + = S + R Q Simplify !!!

19 Latch operation enabled by E E Input sampling enabled by gates Gated Latch R S Q Q E Outputs change when E is low: RESET and SET Otherwise: HOLD Outputs change when E is low: RESET and SET Otherwise: HOLD Latch is level-sensitive, "clocked" by E

20 The J-K Latch J K Q Q + 0 0 0 0HOLD 0 0 1 1 0 1 0 0RESET 0 1 1 0 1 0 0 1SET 1 0 1 1 1 1 0 1 1 1 NEXT STATE TABLE NEW !!! Eliminate the forbidden inputs Introduce “toggling” Eliminate the forbidden inputs Introduce “toggling” 1TOGGLE 0

21 The J-K Latch Schematic R S Q Q’ Latch Q Q J K

22 J-K Latch Characteristic Equation J K Q Q + HOLD 0 0 0 0HOLD 0 0 1 1 RESET 0 1 0 0RESET 0 1 1 0 SET 1 0 0 1SET 1 0 1 1 TOGGLE 1 1 0 1TOGGLE 1 1 1 0 Q JK 00 01 11 10 00011 11001 NEXT STATE TABLE K-map for Q + Simplify !!! Q + = J Q + K Q Characteristic equation

23 Timing Diagram Set Reset Toggle Problem: Keeps toggling! R S Q Q Latch Q Q J K

24 Clock Synchronous Networks Clock a periodic external event (input) Clock a periodic external event (input) INPUTS OUTPUTS CURRENT STATE NEXT STATE Combinational network Storage elements CLOCK CLOCKED synchronizes when current state changes happen keeps system well-behaved makes it easier to design and build large systems synchronizes when current state changes happen keeps system well-behaved makes it easier to design and build large systems

25 Clocking Event a high-to-low or low-to-high transition of the clock Lo-Hi Lo-Hi edge Hi-Lo Hi-Lo edge

26 Setup Time & Hold Time setup timehold time Minimum time input is not changing before (setup time) and after (hold time) the clock event Input Clock T su ThThThTh Clock event There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized There is a timing "window" around the clocking event during which the input must remain stable and unchanged in order to be recognized

27 Do Activity #2 Now Due: End of Class Today RETAIN THE LAST PAGE (#3)!! For Next Class: Bring Randy Katz Textbook, & TTL Data Book Required Reading: – Sec 6.1,6.3,7.1 of Katz This reading is necessary for getting points in the Studio Activity!

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