1. Spring 2002EECS150 - Lec14-seq1 Page 1 EECS150 - Digital Design Lecture 14 - Sequential Circuits I (State Elements) March 12, 2002 John Wawrzynek

2. Spring 2002EECS150 - Lec14-seq1 Page 2 Sequential Circuits Circuit with feedback. Examples: FSM D-type latch How about CL logic with feedback but without register? Sequential circuits exhibit either synchronous or asynchronous behavior: –Synchronous: “state” of the circuit changes at regular intervals controlled by a clock. –Asynchronous: state changes with changing inputs. No clock present or circuit doesn’t wait for it.

3. Spring 2002EECS150 - Lec14-seq1 Page 3 Cross-coupled NOR gates If both R=0 & S=0, then cross-couped NORs equivalent to a stable latch: What happens if R or S or both become = 1? remember,

4. Spring 2002EECS150 - Lec14-seq1 Page 4 Asynchronous State Transition Diagram SR Latch:

5. Spring 2002EECS150 - Lec14-seq1 Page 5 Nand-gate based SR latch

6. Spring 2002EECS150 - Lec14-seq1 Page 6 Level-sensitive SR Latch The input “C” works as an “enable” signal, latch only changes output when C is high. usually connected to clock. Generally, it is not a good idea to use a clock as a logic signal (into gates etc.). This is a special case.

7. Spring 2002EECS150 - Lec14-seq1 Page 7 D-latch Compare to transistor version:

8. Spring 2002EECS150 - Lec14-seq1 Page 8 Flip-flops

9. Spring 2002EECS150 - Lec14-seq1 Page 9 J-K FF Add logic to eliminate “indeterminate” action of RS FF. New action is “toggle” J = “jam” K = “kill”

10. Spring 2002EECS150 - Lec14-seq1 Page 10 J-K Flip-flop from D-FF

11. Spring 2002EECS150 - Lec14-seq1 Page 11 Toggle Flip-flop from D-FF

12. Spring 2002EECS150 - Lec14-seq1 Page 12 Storage Element Taxonomy synchronous asynchronous level-sensitive edge-triggered D-type  n.a. JK-typen.a.  n.a. RS-type  “latch”“flip-flop” “latch”

13. Spring 2002EECS150 - Lec14-seq1 Page 13 Design Example with RS FF With D-type FF state elements, new state iscomputed based on inputs & present state bits - reloaded each cycle. With RS (or JK) FF state elements, inputs are used to determine conditions under which to set or reset state bits. Example: bit-serial adder (LSB first) With D-FF for carry

14. Spring 2002EECS150 - Lec14-seq1 Page 14 Bit-serial adder with RS FF RS FF stores the carry: a b c i c i+1 s Carry kill a’b’ Carry generate ab

15. Spring 2002EECS150 - Lec14-seq1 Page 15 Resets/presets

16. Spring 2002EECS150 - Lec14-seq1 Page 16 Adding Reset/Presets D-type flip-flop from latches: Asynchronous reset in Flip-flop: Either inverter (or both) can be replaced by either NOR gate or NAND gate in the second latch of the flip-flop. The second input to the gate is connected to reset or preset signal. The choice of NOR versus NAND defines the sense of the reset/preset (active-high versus active-low). The choice which inverter to replace defines reset versus preset. Synchronous reset: A similar procedure as above is applied to the first latch of the flip-flop. Additional logic is needed to synchronize the reset signal with the correct level of the clock. D-latch circuit