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EET 1131 Unit 10 Flip-Flops and Registers  Read Kleitz, Chapter 10.  Exam #2 next week.  Homework #10 and Lab #10 due in 1.5 weeks.  Quiz in 1.5 weeks.

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Presentation on theme: "EET 1131 Unit 10 Flip-Flops and Registers  Read Kleitz, Chapter 10.  Exam #2 next week.  Homework #10 and Lab #10 due in 1.5 weeks.  Quiz in 1.5 weeks."— Presentation transcript:

1 EET 1131 Unit 10 Flip-Flops and Registers  Read Kleitz, Chapter 10.  Exam #2 next week.  Homework #10 and Lab #10 due in 1.5 weeks.  Quiz in 1.5 weeks.

2 Combinational Logic versus Sequential Logic  A combinational logic circuit is a circuit whose output depends only on the circuit’s present inputs. (“Has no memory of the past.”)  A sequential logic circuit is a circuit whose output may depend on the circuit’s previous states as well as its present inputs. (“Has a memory.”)

3 Five Latches and Flip-flops Our textbook refers to all five of these as “flip-flops,” but most people call three of them “latches” and two of them “flip-flops.” NameSection in TextbookTextbook’s name for it Sample Chips S-R latch10-1S-R flip-flop74279 Gated S-R latch10-2Gated S-R flip-flop Gated D-latch10-3 and 10-4Gated D flip-flop7475 D flip-flop10-5D flip-flop7474 J-K flip-flop 10-6 (obsolete master- slave variety; ignore it) J-K flip-flop (modern edge- triggered variety) 74LS76

4 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory that stores a single bit. Latches The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAND gates. With NOR gates, the latch responds to active-HIGH inputs. NOR S-R Latch R S Q Q

5 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved The S-R latch is in a stable (latched) condition when both inputs are LOW. S-R Latch R S Q Q Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0). To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW R S Q Q To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW Latch initially RESET Latch initially SET

6 Truth-Table for S-R Latch ( active-high inputs ) SRQ Comments 00Q0Q0 No change RESET 1010 SET 1100 Invalid state

7 Truth-Table for Gated S-R Latch ( active-high inputs ) ENSRQ Comments 0XXQ0Q0 No change 100Q0Q RESET SET Invalid state

8 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved A gated S-R latch is a variation on the basic S-R latch. Gated S-R Latch The gated latch has an additional input, called enable (EN) that must be HIGH in order for the latch to respond to the S and R inputs. R S Q Q EN Show the Q output with relation to the input signals. Assume Q starts LOW. Keep in mind that S and R have effect only when EN is HIGH. S R EN Q

9 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Gated D-Latch The gated D latch is similar to the gated S-R latch but combines the S and R inputs into a single D input as shown: A simple rule for the gated D latch is: Q follows D when the Enable is active. D EN Q Q Q Q D

10 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Gated D-Latch The truth table for the gated D latch summarizes its operation. If EN is LOW, then there is no change in the output and it is latched.

11 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Gated D-Latch Determine the Q output for the gated D latch, given the inputs shown. Notice that the Enable is not active during these times, so the output is latched. Q Q D EN

12 Two Popular Latch Chips  (Quad active-low S-R latch)  7475 (Quad Gated D latch) 7475

13 Level-Triggered versus Edge- Triggered  Gated S-R latches and gated D latches are often called level-triggered devices, because the output can change any time the enable input is at the correct level (HIGH or LOW).  Other devices, such as flip-flops, are edge-triggered, because the output can only change when there is a rising or falling edge on the clock input.

14 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Flip-flops A flip-flop differs from a latch in the manner it changes states. A flip-flop is a clocked device, in which only the clock edge determines when a new bit is entered. The active edge can be positive or negative. Dynamic input indicator Rising edge-triggered Leading edge-triggered Falling edge-triggered Trailing edge-triggered

15 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Flip-flops The truth table for a positive-edge triggered D flip-flop shows an up arrow to remind you that it is sensitive to its D input only on the rising edge of the clock; otherwise it is latched. The truth table for a negative-edge triggered D flip-flop is identical except for the direction of the arrow. (a) Positive-edge triggered (b) Negative-edge triggered

16 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Flip-flops The J-K flip-flop is more versatile than the D flip flop. In addition to the clock input, it has two inputs, labeled J and K. When both J and K = 1, the output changes states (toggles) on the active clock edge (in this case, the rising edge).

17 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Flip-flops Determine the Q output for the J-K flip-flop, assuming Q is initially high. CLK Q K J K J Q Q Notice that the outputs change on the rising edge of the clock. SetToggleSetLatch

18 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Flip-flops Synchronous inputs (for example the D or J-K inputs) affect the output on the triggering edge of the clock. Most flip-flops also have other inputs that are asynchronous, meaning they affect the output independent of the clock. Two such inputs are normally labeled PRE (preset) and CLR (clear). These inputs are usually active LOW, as shown here. Other common names for these pins are SET and RESET. CLK K J Q Q PRE CLR

19 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Flip-flops Determine the Q output for the J-K flip-flop, assuming Q is initially high. CLK K J Q Q PRE CLR SetToggleResetToggle Set Reset Latch CLK K J Q PRE CLR

20 Two Popular Flip-Flop Chips  7474 (Dual D Flip-Flop) 7474  74LS76 (Dual J-K Flip-Flop) 74LS76

21 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Propagation delay time is specified for the rising and falling outputs. It is measured between the 50% level of the clock to the 50% level of the output transition. Flip-flop Timing Characteristics 50% point on triggering edge 50% point 50% point on LOW-to- HIGH transition of Q t PLH t PHL CLK QQ 50% point on HIGH-to- LOW transition of Q The typical propagation delay time for the 74AHC family (CMOS) is 4 ns. Even faster logic is available for specialized applications.

22 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Another propagation delay time specification is the time required for an asynchronous input to cause a change in the output. Again it is measured from the 50% levels. The 74AHC family has specified delay times under 5 ns. Flip-flop Timing Characteristics 50% point t PLH t PHL Q 50% point Q PRE CLR

23 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop. Flip-flop Timing Characteristics Setup time is the minimum time for the data to be present before the clock. Hold time is the minimum time for the data to remain after the clock. CLK D D Set-up time, t s Hold time, t H

24 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Other timing specifications include maximum clock frequency and minimum pulse widths for various inputs. Consult the following datasheet to compare propagation delays, set-up time, hold time, and maximum clock frequency for a 7474, a 74LS74, and a 74S74: 7474 datasheet Flip-flop Timing Characteristics

25 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Flip-flop Applications Principal flip-flop applications are for temporary data storage, as frequency dividers, and in counters (which are covered in detail in Chapter 12). Typically, for data storage applications, a group of flip-flops are connected to parallel data lines and clocked together. We call such a group of flip-flops a register. Data is stored until the next clock pulse. Parallel data input lines Clock Clear Output lines Q0Q0 Q1Q1 Q2Q2 Q3Q3

26 © 2009 Pearson Education, Upper Saddle River, NJ All Rights Reserved Flip-flop Applications For frequency division, it is simple to use a flip-flop in the toggle mode or to chain a series of toggle flip flops to continue to divide by two. One flip-flop will divide f in by 2, two flip-flops will divide f in by 4 (and so on). A side benefit of frequency division is that the output has an exact 50% duty cycle. HIGH CLK K J QAQA K J f in QBQB f out Waveforms: f in f out


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