Presentation on theme: "EET 1131 Unit 10 Flip-Flops and Registers Read Kleitz, Chapter 10. Exam #2 next week. Homework #10 and Lab #10 due in 1.5 weeks. Quiz in 1.5 weeks."— Presentation transcript:
EET 1131 Unit 10 Flip-Flops and Registers Read Kleitz, Chapter 10. Exam #2 next week. Homework #10 and Lab #10 due in 1.5 weeks. Quiz in 1.5 weeks.
Combinational Logic versus Sequential Logic A combinational logic circuit is a circuit whose output depends only on the circuit’s present inputs. (“Has no memory of the past.”) A sequential logic circuit is a circuit whose output may depend on the circuit’s previous states as well as its present inputs. (“Has a memory.”)
Five Latches and Flip-flops Our textbook refers to all five of these as “flip-flops,” but most people call three of them “latches” and two of them “flip-flops.” NameSection in TextbookTextbook’s name for it Sample Chips S-R latch10-1S-R flip-flop74279 Gated S-R latch10-2Gated S-R flip-flop Gated D-latch10-3 and 10-4Gated D flip-flop7475 D flip-flop10-5D flip-flop7474 J-K flip-flop 10-6 (obsolete master- slave variety; ignore it) J-K flip-flop (modern edge- triggered variety) 74LS76
Two Popular Latch Chips (Quad active-low S-R latch) 7475 (Quad Gated D latch) 7475
Level-Triggered versus Edge- Triggered Gated S-R latches and gated D latches are often called level-triggered devices, because the output can change any time the enable input is at the correct level (HIGH or LOW). Other devices, such as flip-flops, are edge-triggered, because the output can only change when there is a rising or falling edge on the clock input.