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EET 1131 Unit 10 Flip-Flops and Registers

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1 EET 1131 Unit 10 Flip-Flops and Registers
Read Kleitz, Chapter 10. Exam #2 next week. Homework #10 and Lab #10 due in 1.5 weeks. Quiz in 1.5 weeks. -Preview Exam #2. -Do Quiz #9. -Handouts: latch practice sheet & flip-flop practice sheet.

2 Combinational Logic versus Sequential Logic
A combinational logic circuit is a circuit whose output depends only on the circuit’s present inputs. (“Has no memory of the past.”) A sequential logic circuit is a circuit whose output may depend on the circuit’s previous states as well as its present inputs. (“Has a memory.”) -Comb: gates, adders, comparators, decoders, enc, MUX, DEMUX, parity. Bell that rings if key in ignition and door open. -Seq: latches, ffs, multivibs, counters, shift regs, memories. Microwave panel that remembers keys pressed before START. 2

3 Five Latches and Flip-flops
Our textbook refers to all five of these as “flip-flops,” but most people call three of them “latches” and two of them “flip-flops.” Name Section in Textbook Textbook’s name for it Sample Chips S-R latch 10-1 S-R flip-flop 74279 Gated S-R latch 10-2 Gated S-R flip-flop Gated D-latch 10-3 and 10-4 Gated D flip-flop 7475 D flip-flop 10-5 7474 J-K flip-flop 10-6 (obsolete master-slave variety; ignore it) 7476 10-7 (modern edge-triggered variety) 74LS76 -Draw symbols of all 5 latches and flip-flops. (Many also available with active-low inputs). 3

4 Latches A latch is a temporary storage device that has two stable states (bistable). It is a basic form of memory that stores a single bit. The S-R (Set-Reset) latch is the most basic type. It can be constructed from NOR gates or NAND gates. With NOR gates, the latch responds to active-HIGH inputs. R Q 1st type of latch: S-R latch. Go thru operation, assuming initially Q=0, ~Q=1, S=0, R=0. Then S=1 & R=0; S=0 & R=0; S=0 & R=1; S=0 & R=0. Q S NOR S-R Latch

5 S-R Latch The S-R latch is in a stable (latched) condition when both inputs are LOW. R S Q 1 Assume the latch is initially RESET (Q = 0) and the inputs are at their inactive level (0). To SET the latch (Q = 1), a momentary HIGH signal is applied to the S input while the R remains LOW. Latch initially RESET 1 R S Q 1 To RESET the latch (Q = 0), a momentary HIGH signal is applied to the R input while the S remains LOW. Latch initially SET 1

6 Truth-Table for S-R Latch (active-high inputs)
Q Comments Q0 No change. 1 RESET SET Invalid state -Do S-R timing diagram. 6

7 Truth-Table for Gated S-R Latch (active-high inputs)
EN S R Q Comments X Q0 No change 1 RESET SET Invalid state -2nd type of latch: Gated S-R latch. -Again, this assumes S and R active-high; another kind has S and R active-low. 7

8 Example Solution Gated S-R Latch
A gated S-R latch is a variation on the basic S-R latch. The gated latch has an additional input, called enable (EN) that must be HIGH in order for the latch to respond to the S and R inputs. S Q EN Example Show the Q output with relation to the input signals. Assume Q starts LOW. Q R Solution Keep in mind that S and R have effect only when EN is HIGH. -Do gated S-R timing diagram. S R EN Q

9 A simple rule for the gated D latch is:
The gated D latch is similar to the gated S-R latch but combines the S and R inputs into a single D input as shown: D Q Q D EN EN Q Q -3rd type of latch: Gated D Latch. A simple rule for the gated D latch is: Q follows D when the Enable is active.

10 Gated D-Latch The truth table for the gated D latch summarizes its operation. If EN is LOW, then there is no change in the output and it is latched.

11 Gated D-Latch Q D Example EN Determine the Q output for the gated D latch, given the inputs shown. Q -Do gated D latch timing diagram. Notice that the Enable is not active during these times, so the output is latched.

12 Two Popular Latch Chips
74279 (Quad active-low S-R latch) 7475 (Quad Gated D latch) 12

13 Level-Triggered versus Edge-Triggered
Gated S-R latches and gated D latches are often called level-triggered devices, because the output can change any time the enable input is at the correct level (HIGH or LOW). Other devices, such as flip-flops, are edge-triggered, because the output can only change when there is a rising or falling edge on the clock input. 13

14 The active edge can be positive or negative.
Flip-flops A flip-flop differs from a latch in the manner it changes states. A flip-flop is a clocked device, in which only the clock edge determines when a new bit is entered. The active edge can be positive or negative. -Many digital systems have a master clock that drives and synchronizes everything in the system. Dynamic input indicator Rising edge-triggered Leading edge-triggered Falling edge-triggered Trailing edge-triggered

15 Flip-flops The truth table for a positive-edge triggered D flip-flop shows an up arrow to remind you that it is sensitive to its D input only on the rising edge of the clock; otherwise it is latched. The truth table for a negative-edge triggered D flip-flop is identical except for the direction of the arrow. -1st type of flip-flop: D flip-flop -Do two D flip-flop timing diagrams. (a) Positive-edge triggered (b) Negative-edge triggered

16 Flip-flops The J-K flip-flop is more versatile than the D flip flop. In addition to the clock input, it has two inputs, labeled J and K. When both J and K = 1, the output changes states (toggles) on the active clock edge (in this case, the rising edge). -2nd type of flip-flop: J-K flip-flop.

17 Example Solution Flip-flops
Q J Example CLK Determine the Q output for the J-K flip-flop, assuming Q is initially high. Q K Notice that the outputs change on the rising edge of the clock. Solution Set Toggle Set Latch CLK -Do first J-K timing diagram. J K Q

18 Flip-flops Synchronous inputs (for example the D or J-K inputs) affect the output on the triggering edge of the clock. Most flip-flops also have other inputs that are asynchronous, meaning they affect the output independent of the clock. PRE Two such inputs are normally labeled PRE (preset) and CLR (clear). These inputs are usually active LOW, as shown here. Other common names for these pins are SET and RESET. Q J -Up to now we’ve only been considering the synchronous inputs. -Note that this involves adding a couple more inputs to the symbol I drew earlier for a J-K flip-flop. -Sometimes the async inputs have different labels (such as ~SET and ~RESET, or ~S and ~R). CLK Q K CLR

19 Example Solution Flip-flops Flip-flops
PRE Flip-flops Flip-flops Q J Example CLK Determine the Q output for the J-K flip-flop, assuming Q is initially high. Q K Solution CLR Set Toggle Set Reset Toggle Latch CLK J -Do second J-K timing diagram. K Set PRE Reset CLR Q

20 Two Popular Flip-Flop Chips
7474 (Dual D Flip-Flop) 74LS76 (Dual J-K Flip-Flop) 20

21 Flip-flop Timing Characteristics
Propagation delay time is specified for the rising and falling outputs. It is measured between the 50% level of the clock to the 50% level of the output transition. 50% point on triggering edge CLK CLK 50% point 50% point on HIGH-to- LOW transition of Q Q Q The material on this slide and on the next three slides is discussed in Chapter 11, which we’ll skip due to time constraints. 50% point on LOW-to-HIGH transition of Q tPLH tPHL The typical propagation delay time for the 74AHC family (CMOS) is 4 ns. Even faster logic is available for specialized applications.

22 Flip-flop Timing Characteristics
Another propagation delay time specification is the time required for an asynchronous input to cause a change in the output. Again it is measured from the 50% levels. The 74AHC family has specified delay times under 5 ns. 50% point CLR 50% point PRE Q 50% point Q 50% point tPHL tPLH

23 Flip-flop Timing Characteristics
Set-up time and hold time are times required before and after the clock transition that data must be present to be reliably clocked into the flip-flop. Setup time is the minimum time for the data to be present before the clock. D CLK Set-up time, ts Hold time is the minimum time for the data to remain after the clock. D CLK Hold time, tH

24 Flip-flop Timing Characteristics
Other timing specifications include maximum clock frequency and minimum pulse widths for various inputs. Consult the following datasheet to compare propagation delays, set-up time, hold time, and maximum clock frequency for a 7474, a 74LS74, and a 74S74: 7474 datasheet

25 Flip-flop Applications
Output lines Q0 Principal flip-flop applications are for temporary data storage, as frequency dividers, and in counters (which are covered in detail in Chapter 12). Q1 Q2 Typically, for data storage applications, a group of flip-flops are connected to parallel data lines and clocked together. We call such a group of flip-flops a register. Data is stored until the next clock pulse. Parallel data input lines Q3 Clock Clear

26 Flip-flop Applications
For frequency division, it is simple to use a flip-flop in the toggle mode or to chain a series of toggle flip flops to continue to divide by two. HIGH HIGH One flip-flop will divide fin by 2, two flip-flops will divide fin by 4 (and so on). A side benefit of frequency division is that the output has an exact 50% duty cycle. QA QB fout J J fin CLK CLK K K fin Waveforms: fout

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