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Chapter 9 Logic Families and Their Characteristics William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education,

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Presentation on theme: "Chapter 9 Logic Families and Their Characteristics William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education,"— Presentation transcript:

1 Chapter 9 Logic Families and Their Characteristics William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

2 The TTL Family Bipolar transistors Two-input NAND gate Multiemitter transistor Totem-pole output stage See Figure 9-1 HIGH level output typically 3.4 V LOW level output typically 0.3 V William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

3 Figure 9-1 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

4 TTL Voltage and Current Ratings Input/Output Current and Fan-Out –source current I OH –sink current I OL –low-level input current I IL –high level input current I IH –See Figure 9-5 and 9-6 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

5 Figure 9-5 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

6 Figure 9-6 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

7 TTL Voltage and Current Ratings Input/Output Voltages and Noise Margin –differences between high level voltages or low level voltages –See Figure 9-7 –See Table 9-1 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

8 Figure 9-7 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

9 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

10 Other TTL Considerations Pulse-Time Parameters –Rise Time from 10% up to 90% level –Fall Time from 90% down to 10% level –Propagation Delay t PLH and t PHL –See Figure 9-10 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

11 Figure 9-10(a) William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

12 Figure 9-10(b) William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

13 Other TTL Considerations Power Dissipation –total power supplied to the IC power terminals Open-Collector Outputs –upper transistor removed from totem-pole –can sink current –can not source current –pull-up resistor used William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

14 Other TTL Considerations Wired-Output Operation –outputs from two or more gates tied together –wired-AND logic - See Figure 9-15 Disposition of Unused Inputs and Unused Gates –open inputs degrade noise immunity –on AND and NAND - tied HIGH –on OR and NOR - tied LOW –unused gates - force outputs HIGH William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

15 Figure 9-15 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

16 Other TTL Considerations Power Supply Decoupling –place 0.01 to 0.1  F capacitor directly across V cc to ground pins –reduce EMI radiation –reduce effect of voltage spikes from power supply William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

17 Improved TTL Series 74HXX series –half the propagation delay –double the power consumption Schottky TTL –low-power (LS) –advanced low-power (ALS) 74FXX –reduced propagation delay William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

18 The CMOS Family MOSFETs –metal oxide semiconductor field-effect transistors –PMOS and NMOS type substrates –See Figure 9-18 –higher packing densities than TTL –millions of memory cells per chip –See Table 9-2 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

19 Figure 9-18 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

20 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

21 The CMOS Family Handling CMOS Devices –avoid electrostatic discharge CMOS availability –4000 Series - original CMOS line –40H00 Series - faster –74C00 Series - pin compatible with TTL –74HC00 and 74HCT00 Series speedy, less power, pin compatible, greater noise immunity and temperature operating range William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

22 The CMOS Family CMOS availability –74- BiCMOS Series - low power and high speed –74-Low Voltage Series See Appendix B supply voltage of 3.3 V –74AHC and 74AHCT Series superior speed low power consumption high output drive current V cc or 3.3 V or 5 V William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

23 The CMOS Family Advanced Very-Low-Voltage CMOS Logic –faster speed –very low operating voltages 3.3, 2.5, 1.8, 1.5 and 1.2 V William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

24 Emitter-Coupled Logic Extremely fast Increased power dissipation Uses differential amplifiers See Figure 9-22 Newer Technologies –integrated injection logic (I 2 L) –silicon-on-sapphire (SOS) –gallium arsenide (GaAs) –Josephen junction circuits William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

25 Figure 9-22 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

26 Comparing Logic Families Performance Specifications –See Table 9-3 Propagation delay versus power –See Figure 9-24 Power supply current versus frequency –See Figure 9-25 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

27 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

28 Figure 9-24 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

29 Figure 9-25 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

30 Interfacing Logic Families TTL to CMOS –See Figure 9-26 –pull-up resistor - see Figure 9-27 CMOS to TTL –See Figure 9-28 and 9-29 Worse-Case Values –See Table 9-4 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

31 Figure 9-26 Figure 9-27 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

32 Figure 9-28 Figure 9-29 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

33 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

34 Interfacing Logic Families Level Shifting –Level-shifter ICs 4049B and 4050B - see Figure B - see Figure 9-32 ECL Interfacing –See Figure 9-33 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

35 Figure 9-31 Figure 9-32 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

36 Figure 9-33 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

37 CPLD Electrical Characteristics Electrical characteristics vary between manufacturers –specifications are in data sheets –MAX 7000 CPLD specifications advanced CMOS interface with 5, 3.3, 2.5, or.8 V devices separate V CC pins for internal operations/input buffers and for I/O drivers William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

38 CPLD Electrical Characteristics EPM728S is part of the MAX7000S series –can interface with 5V and 3.3V devices –see figure 9-35 –provide open drain output –complete TTL and CMOS compatibility –low propagation time –speed/power optimization feature –see figure 9-36 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

39 Figure 9-35 Figure 9-36 William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

40 Summary There are basically three stages of internal circuitry in a TTL (transistor-transistor- logic) IC: input, control, and output. The input current (I IL or I IH ) to an IC gate is a constant value specified by the IC manufacturer. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

41 Summary The output current of an IC gate depends on the size of the load connected to it. Its value cannot exceed the maximum rating of the chip, I OL or I OH. The HIGH- and LOW-level output voltages of the standard TTL family are not 5 V and 0 V but typically are 3.4 V and 0.2 V. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

42 Summary The propagation delay is the length of time that it takes for the output of a gate to respond to a stimulus at its input. The rise and fall times of a pulse describe how long it takes for the voltage to travel between its 10% and 90% levels. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

43 Summary Open-collector outputs are required whenever logic outputs are connected to a common point. Several improved TTL families are available and continue to be introduced each year providing decreased power consumption and decreased propagation delay. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

44 Summary The CMOS family uses complementary metal oxide semiconductor transistors instead of the bipolar transistors used in TTL ICs. Traditionally, the CMOS family consumed less power but was slower than TTL. However, recent advances in both technologies have narrowed the differences. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

45 Summary The BiCMOS family combines the best characteristics of bipolar technology and CMOS technology to provide logic functions that are optimized for the high- speed, low-power characteristics required in microprocessor systems. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

46 Summary A figure of merit of IC families is the product of their propagation delay and power consumption, called the speed-power product (the lower, the better). Emitter-coupled logic (ECL) provides the highest-speed ICs. Its drawback is its very high power consumption. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

47 Summary When interfacing logic families, several considerations must be made. The output voltage level of one family must be high and low enough to meet the input requirements of the receiving family. Also, the output current capability of the driving gate must be high enough for the input draw of the receiving gate or gates. William Kleitz Digital Electronics with VHDL, Quartus® II Version Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.


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