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Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)
–Black-box representation and Truth table shows a logic circuit with input/output and ignores electrical behavior of the circuit Black-box Input Output
–AND gate produces 1 : Only if all of its inputs are 1 –OR gate produces 1 : One or more of its inputs are 1 –NOT gate produces an output that is opposite of its input value
–NAND Gate : Opposite of an AND gates output –NOR Gate : Opposite of an OR gates output
Black-box representationTruth table
–Timing diagram show how the circuit might respond to a time-varying pattern of input signals Lag Input Output
3.3 CMOS Logic Not expected to occur except during signal transition
High resistance : Off Transistor Low resistance : On Transistor NMOS PMOS
NMOS PMOS NMOS
On Z=1 On Z=0
PMOS NMOS PMOS NMOS PMOS NMOS
On Z=0 On Z=1
PMOS F NMOS F D F AND -> Series OR -> Parallel PMOS F NMOS F F = F A C A B B D C D
AND -> Series OR -> Parallel PMOS F NMOS F
Inverter + Inverter
NAND + Inverter More Transistors are needed than NAND
4x3+2 =14 Transistor 6 Transistor 4 Transistor 16 Transistor
4x3+2 =14 Transistor 6 Transistor 4 Transistor 6 Transistor 16 Transistor
3.4 Electrical Behavior of CMOS Circuits
3.5 CMOS Static Electrical Behavior Noise can be added in signals So, There are noise margins
High state Minimum value Low state Maximum value
Not CMOS resistive load
Sink currentSource current
No Transition Time in ideal case (20% ~ 80%) (80% ~ 20%)
3.6 CMOS Dynamic Electrical Behavior Both the speed and the power consumption of a CMOS device depend to a large extent on AC device
High StateLow State
50% Ideal case (No rise and fall times) Propagation delay
3.7 Other CMOS input and Output Structures
Open-drain output requires an external pull-up resistor
Increase because R=1.5K Pull-up Resistor
X Y W
Low output must sink 0.4mA
In high state, typical open-drain outputs have a maximum leakage current 5uA and typical LS-TTL inputs require 20uA of a source current
3.8 CMOS Logic Families High-speed CMOSHigh-speed CMOS, TTL compatible
3.9 Low-Voltage CMOS Logic and Interfacing
Clamp overshoot Clamp diode To Clamp overshoot Clamp undershoot 0.6V -0.6V
G G S D S OFF S D G S D D
3.10 Bipolar Logic
Diode AND Gate Output stage = Totem pole Phase Splitter
Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.
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