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Ch 3. Digital Circuits 3.1 Logic Signals and Gates (When N=1, 2 states)

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–Black-box representation and Truth table shows a logic circuit with input/output and ignores electrical behavior of the circuit Black-box Input Output

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–AND gate produces 1 : Only if all of its inputs are 1 –OR gate produces 1 : One or more of its inputs are 1 –NOT gate produces an output that is opposite of its input value

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–NAND Gate : Opposite of an AND gates output –NOR Gate : Opposite of an OR gates output

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Black-box representationTruth table

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–Timing diagram show how the circuit might respond to a time-varying pattern of input signals Lag Input Output

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3.3 CMOS Logic Not expected to occur except during signal transition

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High resistance : Off Transistor Low resistance : On Transistor NMOS PMOS

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NMOS PMOS NMOS

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CMOS inverter

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On Z=1 On Z=0

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PMOS NMOS PMOS NMOS PMOS NMOS

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On Z=0 On Z=1

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PMOS F NMOS F D F AND -> Series OR -> Parallel PMOS F NMOS F F = F A C A B B D C D

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AND -> Series OR -> Parallel PMOS F NMOS F

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Inverter + Inverter

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NAND + Inverter More Transistors are needed than NAND

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4x3+2 =14 Transistor 6 Transistor 4 Transistor 16 Transistor

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4x3+2 =14 Transistor 6 Transistor 4 Transistor 6 Transistor 16 Transistor

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3.4 Electrical Behavior of CMOS Circuits

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3.5 CMOS Static Electrical Behavior Noise can be added in signals So, There are noise margins

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High state Minimum value Low state Maximum value

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Not CMOS resistive load

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(TTL load)

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Sink currentSource current

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Pull-upPull-down

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No Transition Time in ideal case (20% ~ 80%) (80% ~ 20%)

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3.6 CMOS Dynamic Electrical Behavior Both the speed and the power consumption of a CMOS device depend to a large extent on AC device

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High StateLow State

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High State

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50% Ideal case (No rise and fall times) Propagation delay

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3.7 Other CMOS input and Output Structures

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Open-drain output requires an external pull-up resistor

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Increase because R=1.5K Pull-up Resistor

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X Y W

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Burn !

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Low output must sink 0.4mA

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In high state, typical open-drain outputs have a maximum leakage current 5uA and typical LS-TTL inputs require 20uA of a source current

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3.8 CMOS Logic Families High-speed CMOSHigh-speed CMOS, TTL compatible

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3.9 Low-Voltage CMOS Logic and Interfacing

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Clamp overshoot Clamp diode To Clamp overshoot Clamp undershoot 0.6V -0.6V

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G G S D S OFF S D G S D D

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3.10 Bipolar Logic

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AND

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pnp

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Diode AND Gate Output stage = Totem pole Phase Splitter

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