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**Chapter 10 Digital CMOS Logic Circuits**

10.1 Digital circuit design : An overview 10.2 Design and performance analysis of the CMOS inverter 10.3 CMOS logic gate circuits 10.4 Pseudo- NMOS logic circuits

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**10. 1 Digital circuit Design : An Overview 10. 1**

10.1 Digital circuit Design : An Overview Digital IC technologies and logic circuit families Fig Digital IC technologies and logic circuit families

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**CMOS Replaced NMOS (much lower power dissipation)**

Small size, ease of fabrication Channel length has decreased significantly (as short as 0.06 µm or shorter) Low power dissipation than bipolar logic circuits ( can pack more) . High input impedance of MOS transistors can be used to storage charge temporarily (not in bipolar) High levels of integration for both logic (chapter 10) and memory circuits (chapter 11) . Dynamic logic to further reduce power dissipation and to increase speed performance .

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Bipolar TTL (Transistor-transistor logic) had been used for many years . ECL (Emitter –Coupled Logic) : basic element is the differential BJT pair in chapter 7 . BiCMOS : combines the high speed of BJT’s with low power dissipation of CMOS . GaAs : for very high speed due to the high carrier mobility . Has not demonstrated its potential commercially .

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**Features to be Considered**

Interface circuits for different families Logic flexibility Speed Complex functions Noise immunity Temperature Power dissipation Co$t

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**10. 1. 2 Logic circuit characterization Fig. 10**

Logic circuit characterization Fig Typical voltage transfer (VTC) of a logic inverter .

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**Fig. 10.3 Definitions of propagation delays and switching times of the logic inverter**

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**Fan-In and Fan -Out Fan-in of a gate : number of inputs .**

Fan-out : maximum number of similar gates that a gate can drive while remaining within guaranteed specifications (to keep NMH above certain minimum) .

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**10. 2 Design and performance analysis of the CMOS inverter. 10. 2**

10.2 Design and performance analysis of the CMOS inverter Circuit structure Fig (a) The CMOS inverter and (b) its representation as a pair of switches operated in a complementary fashion .

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Static operation

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Static operation Fig The voltage transfer characteristic (VTC) of the CMOS inverter when QN and QP are matched

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**10.2.3 Dynamic Operation Fig. 10.6 Circuit for analyzing the propagation delay of the inverter**

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**Fig. 10.7 Equivalent circuits for determining the propagation delays**

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**10. 3 CMOS Logic Gate Circuits 10. 3. 1 Basic structure Fig. 10**

10.3 CMOS Logic Gate Circuits Basic structure Fig Representation of a three- input CMOS logic gate

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**Fig. 10.10 Examples of pull –down networks (PDN)**

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**Fig. 10.10 Examples of pull- up networks (PUN)**

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**Fig. 10.11 Usual and alternative symbols for MOSFETs**

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**10.3.2 The Two – Input NOR Gate Fig. 10.12 A two – input CMOS NOR gate**

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**10.3.3 The Two- Input NAND Gate Fig. 10.13 A two-input CMOS NAND gate**

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A Complex Gate

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**10. 3. 5 Obtaining the PUN and the PDN and Vice Versa Fig. 10**

Obtaining the PUN and the PDN and Vice Versa Fig CMOS realization of a complex gate

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**10. 3. 6 The Exclusive- OR Function Fig. 10**

The Exclusive- OR Function Fig Realization of the exclusive –OR (XOR) function .

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**10.3.8 Transistor Sizing Fig. 10.16 Proper transistor sizing for a four- input NOR gate**

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**Fig. 10. 17 Proper transistor sizing for a four- input NAND gate**

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**Fig. 10.18 Circuit for Example 10.2**

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**10. 4 Pseudo- NMOS Logic Circuits 10. 4**

10.4 Pseudo- NMOS Logic Circuits The pseudo – NMOS inverter Fig (a) The pseudo- NMOS logic inverter . (b) The enhancement load NMOS inverter (c) The depletion- load NMOS inverter

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**Fig. 4-2 . The enhancement-type NMOS transistor with applied voltage**

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**The I-V characteristic of MOSFET**

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**The n- channel depletion –type MOSFET**

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**The depletion type n-channel MOSFET**

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**10. 4. 2 Static Characteristics Fig. 10**

Static Characteristics Fig Graphical construction to determine the VTC of the inverter

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**Fig. 10.21 VTC for the pseudo- NMOS inverter .**

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Dynamic Operation

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