11 CMOS Electrical Characteristics Digital analysis works only if circuits are operated in spec:Power supply voltageTemperatureInput-signal qualityOutput loadingMust do some “analog” analysis to prove that circuits are operated in spec.Fanout specsTiming analysis (setup and hold times)
12 DC LoadingAn output must sink current from a load when the output is in the LOW state.An output must source current to a load when the output is in the HIGH state.
13 Output-voltage dropsResistance of “off” transistor is > 1 Megohm, but resistance of “on” transistor is nonzero,Voltage drops across “on” transistor, V = IRFor “CMOS” loads, current and voltage drop are negligible.For TTL inputs, LEDs, terminations, or other resistive loads, current and voltage drop are significant and must be calculated.
14 Example loading calculation Need to know “on” and “off” resistances of output transistors, and know the characteristics of the load.
16 Limitation on DC loadIf too much load, output voltage will go outside of valid logic-voltage range.VOHmin, VIHminVOLmax, VILmax
17 Output-drive specsVOLmax and VOHmin are specified for certain output-current values, IOLmax and IOHmax.No need to know details about the output circuit, only the load.
18 Input-loading specsEach gate input requires a certain amount of current to drive it in the LOW state and in the HIGH state.IIL and IIHThese amounts are specified by the manufacturer.Fanout calculation(LOW state) The sum of the IIL values of the driven inputs may not exceed IOLmax of the driving output.(HIGH state) The sum of the IIH values of the driven inputs may not exceed IOHmax of the driving output.Need to do Thevenin-equivalent calculation for non-gate loads (LEDs, termination resistors, etc.)
27 TTL differences from CMOS Asymmetric input and output characteristics.Inputs source significant current in the LOW state, leakage current in the HIGH state.Output can handle much more current in the LOW state (saturated transistor).Output can source only limited current in the HIGH state (resistor plus partially-on transistor).TTL has difficulty driving “pure” CMOS inputs because VOH = 2.4 V (except “T” CMOS).
28 AC LoadingAC loading has become a critical design factor as industry has moved to pure CMOS systems.CMOS inputs have very high impedance, DC loading is negligible.CMOS inputs and related packaging and wiring have significant capacitance.Time to charge and discharge capacitance is a major component of delay.
35 Transition-time considerations Higher capacitance ==> more delayHigher on-resistance ==> more delayLower on-resistance requires bigger transistorsSlower transition times ==> more power dissipation (output stage partially shorted)Faster transition times ==> worse transmission-line effects (Chapter 11)Higher capacitance ==> more power dissipation (CV2f power), regardless of rise and fall time
36 Open-drain outputsNo PMOS transistor, use resistor pull-up
37 What good is it?Open-drain busProblem -- really bad rise time
38 Open-drain transition times Pull-up resistance is larger than a PMOS transistor’s “on” resistance.Can reduce rise time by reducing pull-up resistor valueBut not too much