Presentation on theme: "Logic Families and Their Characteristics"— Presentation transcript:
1Logic Families and Their Characteristics Chapter 9Logic Families and Their Characteristics1
2Objectives You should be able to: Analyze internal circuitry of a TTL NAND gate for both HIGH and LOW output states.Determine IC input and output voltage and current ratings from the manufacturer’s data manual.Explain gate loading, fan-out, noise margin, and time parameters.2
3Objectives (Continued) Design wired-output circuits using open-collector TTL gates.Discuss the differences and proper use of the various subfamilies within both TTL and CMOS ICs.Describe the reasoning and various techniques for interfacing between the TTL, CMOS, and ECL families of ICs.3
4The TTL Family Bipolar transistors Physical model Symbol Diode equivalent4
5The TTL Family Two-input NAND gate Multi-emitter transistor Totem-pole output stageHIGH level output typically 3.4 VLOW level output typically 0.3 V5
7TTL Voltage and Current Ratings Input/output current and fan-outSource current – IOHSink current – IOLLow-level input current – IILHigh level input current – IIH7
8TTL Voltage and Current Ratings Example of TTL gate sinking input currents from two gate inputs using logic symbols8
9TTL Voltage and Current Ratings Example of TTL gate sinking input currents from two gate inputs using schematic symbols9
10TTL Voltage and Current Ratings Example of TTL gate sourcing current to two gate inputs using logic symbols10
11TTL Voltage and Current Ratings Example of TTL gate sourcing current to two gate inputs using schematic symbols11
12TTL Voltage and Current Ratings Summary of I/O current and fan-out:Low-level input current IIL = 1.6 mA (-1600 μA)High level input current IIH = 40 μA(The minus sign indicates current leaving the gate)IOL – low-level output current = 16 mA (16,000 μA)IOH – high-level output current = -400 μA (-800 μA for some)(Max capability of a gate to sink or source current)Fan-out is max number of gate inputs that can be connected to a standard ttl gate output.Typically fan-out = 10.12
13TTL Voltage and Current Ratings Input/Output Voltages and Noise MarginNoise margin: The difference between high level voltages and low level voltages13
14TTL Voltage and Current Ratings Input/Output Voltages and Noise Margin (graphical representation)14
15Discussion PointLocate the voltage and current ratings covered so far on the typical data sheet given in Figure 9-8.16
19Other TTL Considerations Pulse-Time ParametersRise Time – Measured from 10% level to 90% level20
20Other TTL Considerations Pulse-Time ParametersFall Time – Measured from 90% level to 10% level21
21Other TTL Considerations Pulse-Time ParametersPropagation Delay (tPLH and tPHL)22
22Other TTL Considerations Power dissipationTotal power supplied to the IC power terminalsOpen-collector outputsUpper transistor removed from totem-poleCan sink currentCan not source currentPull-up resistor used23
23Other TTL Considerations Wired-output operationOutputs from two or more gates tied togetherWired-AND logic24
24Figure 9–16 Wired-ANDing of open-collector gates for Example 9–4: (a) original circuit and (b) alternative gate representations used for clarity.
25Figure 9–13 (continued) TTL NAND with an open-collector output: (a) circuitry; (b) truth table.
26Figure 9–13 TTL NAND with an open-collector output: (a) circuitry; (b) truth table.
27Figure 9–14 Using a pull-up resistor with an open-collector output Figure 9–14 Using a pull-up resistor with an open-collector output. (a) Adding a pull-up resistor to a NAND gate. (b) When Q4 inside the NAND is on, Vout ≈ 0 V. (c) When Q4 is off, the pull-up resistor provides ≈ 5 V to Vout.
28Other TTL Considerations Disposition of unused inputs and unused gatesOpen inputs degrade noise immunityOn AND and NAND – tied HIGHOn OR and NOR – tied LOWUnused gates – force outputs HIGH25
29Other TTL Considerations Power supply decouplingConnecing 0.01 to 0.1 F capacitor between VCC and ground pinsReduces EMI radiationReduces effect of voltage spikes from power supply26
30Improved TTL Series 74HXX series Schottky TTL 74FXX Half the propagation delayDouble the power consumptionSchottky TTLLow-power (LS)Advanced low-power (ALS)74FXXReduced propagation delay27
35Figure 9–19 CMOS inverter formed from complementary N-channel/P-channel transistors.
36The CMOS Family Handling CMOS devices CMOS availability Avoid electrostatic dischargeCMOS availability4000 series - original CMOS line40H00 series - faster74C00 series - pin compatible with TTL74HC00 and 74HCT00 seriesSpeedy, less power, pin compatible, greater noise immunity and temperature operating range30
37Figure 9–21 Wearing a commercially available wrist strap dissipates static charges from the technician’s body to a ground connection while handling CMOS ICs.
38The CMOS Family CMOS availability 74- biCMOS series - low power and high speed74-low voltage seriesSee appendix BNominal supply voltage of 3.3 V74AHC and 74AHCT seriesSuperior speedLow power consumptionHigh output drive current31
39The CMOS Family 74AVC advanced very-low-voltage CMOS logic Faster speedVery low operating voltages3.3 V, 2.5 V, 1.8 V, 1.5 V and 1.2 V32
40Emitter-Coupled Logic Extremely fastIncreased power dissipationUses differential amplifiersFigure 9-2233
53SummaryThere are basically three stages of internal circuitry in a TTL (transistor-transistor-logic) IC: input, control, and output.The input current (IIL or IIH) to an IC gate is a constant value specified by the IC manufacturer.46
54SummaryThe output current of an IC gate depends on the size of the load connected to it. Its value cannot exceed the maximum rating of the chip, IOL or IOH.The HIGH- and LOW-level output voltages of the standard TTL family are not 5 V and 0 V but typically are 3.4 V and 0.2 V.47
55SummaryThe propagation delay is the length of time that it takes for the output of a gate to respond to a stimulus at its input.The rise and fall times of a pulse describe how long it takes for the voltage to travel between its 10% and 90% levels.48
56SummaryOpen-collector outputs are required whenever logic outputs are connected to a common point.Several improved TTL families are available and continue to be introduced each year providing decreased power consumption and decreased propagation delay.49
57SummaryThe CMOS family uses complementary metal oxide semiconductor transistors instead of the bipolar transistors used in TTL ICs. Traditionally, the CMOS family consumed less power but was slower than TTL. However, recent advances in both technologies have narrowed the differences.50
58SummaryThe BiCMOS family combines the best characteristics of bipolar technology and CMOS technology to provide logic functions that are optimized for the high-speed, low-power characteristics required in microprocessor systems.51
59SummaryA figure of merit of IC families is the product of their propagation delay and power consumption, called the speed-power product (the lower, the better).Emitter-coupled logic (ECL) provides the highest-speed ICs. Its drawback is its very high power consumption.52
60SummaryWhen interfacing logic families, several considerations must be made. The output voltage level of one family must be high and low enough to meet the input requirements of the receiving family. Also, the output current capability of the driving gate must be high enough for the input draw of the receiving gate or gates.53