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Chapter 9 Logic Families and Their Characteristics 1.

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1 Chapter 9 Logic Families and Their Characteristics 1

2 Objectives You should be able to: Analyze internal circuitry of a TTL NAND gate for both HIGH and LOW output states. Analyze internal circuitry of a TTL NAND gate for both HIGH and LOW output states. Determine IC input and output voltage and current ratings from the manufacturers data manual. Determine IC input and output voltage and current ratings from the manufacturers data manual. Explain gate loading, fan-out, noise margin, and time parameters. Explain gate loading, fan-out, noise margin, and time parameters. 2

3 Objectives (Continued) Design wired-output circuits using open-collector TTL gates. Design wired-output circuits using open-collector TTL gates. Discuss the differences and proper use of the various subfamilies within both TTL and CMOS ICs. Discuss the differences and proper use of the various subfamilies within both TTL and CMOS ICs. Describe the reasoning and various techniques for interfacing between the TTL, CMOS, and ECL families of ICs. Describe the reasoning and various techniques for interfacing between the TTL, CMOS, and ECL families of ICs. 3

4 The TTL Family Bipolar transistors Bipolar transistors Physical model Physical model Symbol Symbol Diode equivalent Diode equivalent 4

5 The TTL Family Two-input NAND gate Two-input NAND gate Multi-emitter transistor Multi-emitter transistor Totem-pole output stage Totem-pole output stage HIGH level output typically 3.4 V HIGH level output typically 3.4 V LOW level output typically 0.3 V LOW level output typically 0.3 V 5

6 The TTL Family 7400 two-input NAND gate 7400 two-input NAND gate 6

7 TTL Voltage and Current Ratings Input/output current and fan-out Input/output current and fan-out Source current – I OH Source current – I OH Sink current – I OL Sink current – I OL Low-level input current – I IL Low-level input current – I IL High level input current – I IH High level input current – I IH 7

8 TTL Voltage and Current Ratings Example of TTL gate sinking input currents from two gate inputs using logic symbols Example of TTL gate sinking input currents from two gate inputs using logic symbols 8

9 TTL Voltage and Current Ratings Example of TTL gate sinking input currents from two gate inputs using schematic symbols Example of TTL gate sinking input currents from two gate inputs using schematic symbols 9

10 TTL Voltage and Current Ratings Example of TTL gate sourcing current to two gate inputs using logic symbols Example of TTL gate sourcing current to two gate inputs using logic symbols 10

11 TTL Voltage and Current Ratings Example of TTL gate sourcing current to two gate inputs using schematic symbols Example of TTL gate sourcing current to two gate inputs using schematic symbols 11

12 TTL Voltage and Current Ratings Summary of I/O current and fan-out: Summary of I/O current and fan-out: Low-level input current I IL = 1.6 mA (-1600 μA) Low-level input current I IL = 1.6 mA (-1600 μA) High level input current I IH = 40 μA High level input current I IH = 40 μA (The minus sign indicates current leaving the gate) (The minus sign indicates current leaving the gate) I OL – low-level output current = 16 mA (16,000 μA) I OL – low-level output current = 16 mA (16,000 μA) I OH – high-level output current = -400 μA (-800 μA for some) I OH – high-level output current = -400 μA (-800 μA for some) (Max capability of a gate to sink or source current) (Max capability of a gate to sink or source current) Fan-out is max number of gate inputs that can be connected to a standard ttl gate output. Fan-out is max number of gate inputs that can be connected to a standard ttl gate output. Typically fan-out = 10. Typically fan-out =

13 TTL Voltage and Current Ratings Input/Output Voltages and Noise Margin Input/Output Voltages and Noise Margin Noise margin: The difference between high level voltages and low level voltages Noise margin: The difference between high level voltages and low level voltages 13

14 TTL Voltage and Current Ratings Input/Output Voltages and Noise Margin (graphical representation) Input/Output Voltages and Noise Margin (graphical representation) 14

15 Discussion Point Locate the voltage and current ratings covered so far on the typical data sheet given in Figure 9-8. Locate the voltage and current ratings covered so far on the typical data sheet given in Figure

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19 Other TTL Considerations Pulse-Time Parameters Pulse-Time Parameters Rise Time – Measured from 10% level to 90% level Rise Time – Measured from 10% level to 90% level 20

20 Other TTL Considerations Pulse-Time Parameters Pulse-Time Parameters Fall Time – Measured from 90% level to 10% level Fall Time – Measured from 90% level to 10% level 21

21 Other TTL Considerations Pulse-Time Parameters Pulse-Time Parameters Propagation Delay (t PLH and t PHL ) Propagation Delay (t PLH and t PHL ) 22

22 Other TTL Considerations Power dissipation Power dissipation Total power supplied to the IC power terminals Total power supplied to the IC power terminals Open-collector outputs Open-collector outputs Upper transistor removed from totem-pole Upper transistor removed from totem-pole Can sink current Can sink current Can not source current Can not source current Pull-up resistor used Pull-up resistor used 23

23 Other TTL Considerations Wired-output operation Wired-output operation Outputs from two or more gates tied together Outputs from two or more gates tied together Wired-AND logic Wired-AND logic 24

24 Figure 9–16 Wired-ANDing of open-collector gates for Example 9–4: (a) original circuit and (b) alternative gate representations used for clarity.

25 Figure 9–13 (continued) TTL NAND with an open-collector output: (a) circuitry; (b) truth table.

26 Figure 9–13 TTL NAND with an open-collector output: (a) circuitry; (b) truth table.

27 Figure 9–14 Using a pull-up resistor with an open-collector output. (a) Adding a pull-up resistor to a NAND gate. (b) When Q 4 inside the NAND is on, V out 0 V. (c) When Q 4 is off, the pull-up resistor provides 5 V to V out.

28 Other TTL Considerations Disposition of unused inputs and unused gates Disposition of unused inputs and unused gates Open inputs degrade noise immunity Open inputs degrade noise immunity On AND and NAND – tied HIGH On AND and NAND – tied HIGH On OR and NOR – tied LOW On OR and NOR – tied LOW Unused gates – force outputs HIGH Unused gates – force outputs HIGH 25

29 Other TTL Considerations Power supply decoupling Power supply decoupling Connecing 0.01 to 0.1 F capacitor between V CC and ground pins Connecing 0.01 to 0.1 F capacitor between V CC and ground pins Reduces EMI radiation Reduces EMI radiation Reduces effect of voltage spikes from power supply Reduces effect of voltage spikes from power supply 26

30 Improved TTL Series 74HXX series 74HXX series Half the propagation delay Half the propagation delay Double the power consumption Double the power consumption Schottky TTL Schottky TTL Low-power (LS) Low-power (LS) Advanced low-power (ALS) Advanced low-power (ALS) 74FXX 74FXX Reduced propagation delay Reduced propagation delay 27

31 Figure 9–17 Schottky-clamped transistor: (a) Schottky diode reduces stored charges and (b) symbol.

32 The CMOS Family MOSFETs MOSFETs Metal oxide semiconductor field-effect transistors Metal oxide semiconductor field-effect transistors PMOS and NMOS type substrates PMOS and NMOS type substrates 28

33 The CMOS Family MOSFETs MOSFETs Higher packing densities than TTL Higher packing densities than TTL Millions of memory cells per chip Millions of memory cells per chip See Table 9-2 in your text See Table 9-2 in your text 29

34 Table 9–2 Basic MOSFET switching characteristics.

35 Figure 9–19 CMOS inverter formed from complementary N-channel/P-channel transistors.

36 The CMOS Family Handling CMOS devices Handling CMOS devices Avoid electrostatic discharge Avoid electrostatic discharge CMOS availability CMOS availability 4000 series - original CMOS line 4000 series - original CMOS line 40H00 series - faster 40H00 series - faster 74C00 series - pin compatible with TTL 74C00 series - pin compatible with TTL 74HC00 and 74HCT00 series 74HC00 and 74HCT00 series Speedy, less power, pin compatible, greater noise immunity and temperature operating range Speedy, less power, pin compatible, greater noise immunity and temperature operating range 30

37 Figure 9–21 Wearing a commercially available wrist strap dissipates static charges from the technicians body to a ground connection while handling CMOS ICs.

38 The CMOS Family CMOS availability CMOS availability 74- biCMOS series - low power and high speed 74- biCMOS series - low power and high speed 74-low voltage series 74-low voltage series See appendix B See appendix B Nominal supply voltage of 3.3 V Nominal supply voltage of 3.3 V 74AHC and 74AHCT series 74AHC and 74AHCT series Superior speed Superior speed Low power consumption Low power consumption High output drive current High output drive current 31

39 The CMOS Family 74AVC advanced very-low-voltage CMOS logic 74AVC advanced very-low-voltage CMOS logic Faster speed Faster speed Very low operating voltages Very low operating voltages 3.3 V, 2.5 V, 1.8 V, 1.5 V and 1.2 V 3.3 V, 2.5 V, 1.8 V, 1.5 V and 1.2 V 32

40 Emitter-Coupled Logic Extremely fast Extremely fast Increased power dissipation Increased power dissipation Uses differential amplifiers Uses differential amplifiers Figure

41 Emitter-Coupled Logic Newer technologies Newer technologies Integrated injection logic (I 2 L) Integrated injection logic (I 2 L) Silicon-on-sapphire (SOS) Silicon-on-sapphire (SOS) Gallium arsenide (GaAs) Gallium arsenide (GaAs) Josephson junction circuits Josephson junction circuits 34

42 Comparing Logic Families Performance specifications Performance specifications 35

43 Comparing Logic Families Propagation delay versus power Propagation delay versus power 36

44 Comparing Logic Families Power supply current versus frequency Power supply current versus frequency 37

45 Interfacing Logic Families TTL to CMOS TTL to CMOS 38

46 Interfacing Logic Families TTL to CMOS TTL to CMOS Pull-up resistor Pull-up resistor 39

47 Interfacing Logic Families CMOS to TTL CMOS to TTL 40

48 Interfacing Logic Families CMOS to TTL CMOS to TTL 41

49 Interfacing Logic Families Worse-case values Worse-case values See Table 9-4 in your text. See Table 9-4 in your text. 42

50 Interfacing Logic Families Level Shifting Level Shifting Level-shifter ICs: 4049B and 4050B Level-shifter ICs: 4049B and 4050B 43

51 Interfacing Logic Families Level Shifting Level Shifting Level-shifter ICs: 4504B Level-shifter ICs: 4504B 44

52 Interfacing Logic Families ECL Interfacing ECL Interfacing 45

53 Summary There are basically three stages of internal circuitry in a TTL (transistor-transistor-logic) IC: input, control, and output. There are basically three stages of internal circuitry in a TTL (transistor-transistor-logic) IC: input, control, and output. The input current (I IL or I IH ) to an IC gate is a constant value specified by the IC manufacturer. The input current (I IL or I IH ) to an IC gate is a constant value specified by the IC manufacturer. 46

54 Summary The output current of an IC gate depends on the size of the load connected to it. Its value cannot exceed the maximum rating of the chip, I OL or I OH. The output current of an IC gate depends on the size of the load connected to it. Its value cannot exceed the maximum rating of the chip, I OL or I OH. The HIGH- and LOW-level output voltages of the standard TTL family are not 5 V and 0 V but typically are 3.4 V and 0.2 V. The HIGH- and LOW-level output voltages of the standard TTL family are not 5 V and 0 V but typically are 3.4 V and 0.2 V. 47

55 Summary The propagation delay is the length of time that it takes for the output of a gate to respond to a stimulus at its input. The propagation delay is the length of time that it takes for the output of a gate to respond to a stimulus at its input. The rise and fall times of a pulse describe how long it takes for the voltage to travel between its 10% and 90% levels. The rise and fall times of a pulse describe how long it takes for the voltage to travel between its 10% and 90% levels. 48

56 Summary Open-collector outputs are required whenever logic outputs are connected to a common point. Open-collector outputs are required whenever logic outputs are connected to a common point. Several improved TTL families are available and continue to be introduced each year providing decreased power consumption and decreased propagation delay. Several improved TTL families are available and continue to be introduced each year providing decreased power consumption and decreased propagation delay. 49

57 Summary The CMOS family uses complementary metal oxide semiconductor transistors instead of the bipolar transistors used in TTL ICs. Traditionally, the CMOS family consumed less power but was slower than TTL. However, recent advances in both technologies have narrowed the differences. The CMOS family uses complementary metal oxide semiconductor transistors instead of the bipolar transistors used in TTL ICs. Traditionally, the CMOS family consumed less power but was slower than TTL. However, recent advances in both technologies have narrowed the differences. 50

58 Summary The BiCMOS family combines the best characteristics of bipolar technology and CMOS technology to provide logic functions that are optimized for the high-speed, low- power characteristics required in microprocessor systems. The BiCMOS family combines the best characteristics of bipolar technology and CMOS technology to provide logic functions that are optimized for the high-speed, low- power characteristics required in microprocessor systems. 51

59 Summary A figure of merit of IC families is the product of their propagation delay and power consumption, called the speed-power product (the lower, the better). A figure of merit of IC families is the product of their propagation delay and power consumption, called the speed-power product (the lower, the better). Emitter-coupled logic (ECL) provides the highest-speed ICs. Its drawback is its very high power consumption. Emitter-coupled logic (ECL) provides the highest-speed ICs. Its drawback is its very high power consumption. 52

60 Summary When interfacing logic families, several considerations must be made. The output voltage level of one family must be high and low enough to meet the input requirements of the receiving family. Also, the output current capability of the driving gate must be high enough for the input draw of the receiving gate or gates. When interfacing logic families, several considerations must be made. The output voltage level of one family must be high and low enough to meet the input requirements of the receiving family. Also, the output current capability of the driving gate must be high enough for the input draw of the receiving gate or gates. 53


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