Presentation is loading. Please wait.

Presentation is loading. Please wait.

Chapter 6 Exclusive-OR and Exclusive-NOR Gates Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William.

Similar presentations


Presentation on theme: "Chapter 6 Exclusive-OR and Exclusive-NOR Gates Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William."— Presentation transcript:

1 Chapter 6 Exclusive-OR and Exclusive-NOR Gates Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

2 The Exclusive-OR Gate HIGH output if one input or the other input is HIGH, but not both. Logic Symbol - See Figure 6-3 Truth Table - See Table 6-1 Boolean equation –X = AB + AB Comparator Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

3 Figure 6-3 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

4 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

5 The Exclusive-NOR Gate The complement of the exclusive-OR Logic Symbol - See Figure 6-4 Truth Table - See Table 6-2 Boolean equation –X = AB + A B Comparator Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

6 Figure 6-4 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

7 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

8 Parity Generator / Checker Electrical noise in the transmission of binary information can cause errors Parity can detect these types of errors Parity systems –odd parity –even parity Adds a bit to the binary information Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

9 Parity Generator / Checker See Figure 6-8 Error indicator output Even- and odd-parity generators –see Figure 6-9 Integrated-Circuit Parity Generator/Checker –74280 TTL IC –Function Table - see Figure 6-12 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

10 Figure 6-8 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

11 Figure 6-9 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

12 Figure 6-12 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

13 System Design Applications See example 6-5, 6-6, and 6-7 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

14 Figure 6-13 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

15 Figure 6-14 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

16 Figure 6-15 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

17 CPLD Design Applications with VHDL Used to simulate combinations of inputs and observe the resulting output to check for proper design operation. See examples 6-8, 6-9, and 6-10 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

18 CPLD Design Applications with VHDL Example 6-8, the parity geneator using the Quartus II Macrofunction –build a block design file –build a vector waveform file –provide a binary count on the 9 bit input so that several combinations of odd and even parity are generated Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

19 Figure 6-16 Figure 6-17 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

20 CPLD Design Applications with VHDL Example 6-9, parallel binary comparator –reproduce the parallel binary comparator of example 6-6 –complete the circuit using bdf and VHDL entry methods –test operation Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

21 Figure 6-18 Figure 6-19 Figure 6-20 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

22 CPLD Design Applications with VHDL Example 6-10, CPLD controlled inverter –reproduce the controlled inverter of example 6-7 –complete the circuit using bdf and VHDL entry methods –test operation Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

23 Figure 6-21 Figure 6-22 Figure 6-23 Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

24 Summary The exclusive-OR gate outputs a HIGH if one or the other inputs, but not both, is HIGH. The exclusive-NOR gate outputs a HIGH if both inputs are HIGH or if both inputs are LOW. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

25 Summary A parity bit is commonly used for error detection during the transmission of digital signals. Exclusive-OR and NOR gates are used in applications such as parity checking, binary comparison and controlled complementing circuits. Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version

26 Summary CPLDs can be used to implement circuits containing the exclusive gates Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved. William Kleitz Digital Electronics with VHDL, Quartus® II Version


Download ppt "Chapter 6 Exclusive-OR and Exclusive-NOR Gates Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey 07458 All rights reserved. William."

Similar presentations


Ads by Google