2Outline Floorplanning Sequencing Sequencing Element Design Max and Min-DelayClock SkewTime BorrowingTwo-Phase Clocking
3Project Strategy Proposal Floorplan Schematic Layout Specifies inputs, outputs, relation between themFloorplanBegins with block diagramAnnotate dimensions and location of each blockRequires detailed paper designSchematicMake paper design simulate correctlyLayoutPhysical design, DRC, ERC
4Floorplan How do you estimate block areas? Begin with block diagramEach block hasInputsOutputsFunction (draw schematic)Type: array, datapath, random logicEstimation depends on type of logic
5Area Estimation Arrays: Datapaths Random logic Layout basic cell Calculate core area from # of cellsAllow area for decoders, column circuitryDatapathsSketch slice planCount area of cells from cell libraryEnsure wiring is possibleRandom logicEvaluate complexity of the design you have done
6Typical Layout Densities Typical numbers of high-quality layoutAllocate space for big wiring channelsElementAreaRandom logic (2 metal layers)l2 / transistorDatapath250 – 750 l2 / transistorSRAM1000 l2 / bitDRAM100 l2 / bitROM
7Sequencing Combinational logic output depends on current inputs Sequential logicoutput depends on current and previous inputsRequires separating previous, current, futureCalled state or tokensEx: FSM, pipeline
8Sequencing Cont.If tokens moved through pipeline at constant speed, no sequencing elements would be necessaryEx: fiber-optic cableLight pulses (tokens) are sent down cableNext pulse sent before first reaches end of cableNo need for hardware to separate pulsesBut dispersion sets min time between pulsesThis is called wave pipelining in circuitsIn most circuits, dispersion is highDelay fast tokens so they don’t catch slow ones.
9Sequencing OverheadUse flip-flops to delay fast tokens so they move through exactly one stage each cycle.Inevitably adds some delay to the slow tokensMakes circuit slower than just the logic delayCalled sequencing overheadSome people call this clocking overheadBut it applies to asynchronous circuits tooInevitable side effect of maintaining sequence
10Sequencing Elements Latch: Level sensitive transparent latch, D latch Flip-flop: edge triggeredmaster-slave flip-flop, D flip-flop, D registerTiming DiagramsTransparentOpaqueEdge-trigger
26Min-Delay: 2-Phase Latches Hold time reduced by nonoverlapParadox: hold applies twice each cycle, vs. only once for flops.But a flop is made of two latches!
27Min-Delay: Pulsed Latches Hold time increased by pulse width
28Time Borrowing In a flop-based system: In a latch-based system Data launches on a rising edgeMust setup before next rising edgeIf it arrives late, system failsIf it arrives early, time is wastedFlops have hard edgesIn a latch-based systemData can pass through latch while transparentLong cycle of logic can borrow time into nextAs long as each loop completes in one cycle
34Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speedAn easy way to guarantee hold times is to use 2-phase latches with big nonoverlap timesCall these clocks f1, f2 (ph1, ph2)
35Safe Flip-FlopIt’s possible to use flip-flop with nonoverlapping clocksVery slow – nonoverlap adds to setup timeBut no hold timesIn industry, use a better timing analyzerAdd buffers to slow signals if hold time is at risk
36Summary 2-Phase Transparent Latches: Lots of skew tolerance and time borrowingFlip-Flops:Very easy to use, supported by all toolsPulsed Latches:Fast, some skew tol & borrow, hold time risk