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S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 24: Sequential Circuit Design (2/3) Prof. Sherief Reda Division of Engineering,

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Presentation on theme: "S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 24: Sequential Circuit Design (2/3) Prof. Sherief Reda Division of Engineering,"— Presentation transcript:

1 S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 24: Sequential Circuit Design (2/3) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources: Weste/Addison Wesley – Rabaey/Pearson]

2 S. Reda EN160 SP’07 A Flip-flop is a pair of back-to-back latches

3 S. Reda EN160 SP’07 Sequencing timing terminology t pd Logic Prop. Delay t pdq Latch D-Q Prop Delay t cd Logic Cont. Delay t pcq Latch D-Q Cont. Delay t pcq Latch/Flop Clk-Q Prop Delay t setup Latch/Flop Setup Time t ccq Latch/Flop Clk-Q Cont. Delay t hold Latch/Flop Hold Time

4 S. Reda EN160 SP’07 Max-Delay (setup) constraint: Flip-flops

5 S. Reda EN160 SP’07 Max-Delay (setup) constraint: 2-phase latches

6 S. Reda EN160 SP’07 Max-Delay (setup) constraint: Pulsed latches

7 S. Reda EN160 SP’07 Example Determine the maximum logic propagation delay available within a 500ps clock cycle Using Flip-flops: Using Two-phase transparent latches: Pulsed latches with 80ps pulse width: t pd =500-(65+50) = 385ps t pd =500-2*40 = 420ps t pd = = 460ps

8 S. Reda EN160 SP’07 Min-delay (hold) constraint: Flip-flip

9 S. Reda EN160 SP’07 Min-delay (hold) constraint: 2-phase latches

10 S. Reda EN160 SP’07 Min-delay (hold) constraint: Pulsed latch

11 S. Reda EN160 SP’07 Example Determine the minimum logic contamination delay in each clock cycle (or half-cycle, for two-phase latches) Using Flip-flops: Using Two-phase transparent latches (duty 50%): Pulsed latches with 80ps pulse width: t cd =30-35 = 0ps t cd = =75ps Using Two-phase transparent latches (60ps nonoverlap): t cd = =0ps


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