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Introduction to CMOS VLSI Design Sequential Circuits.

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Presentation on theme: "Introduction to CMOS VLSI Design Sequential Circuits."— Presentation transcript:

1 Introduction to CMOS VLSI Design Sequential Circuits

2 CMOS VLSI Design2 Outline  Sequencing  Sequencing Element Design  Max and Min-Delay  Clock Skew  Time Borrowing  Two-Phase Clocking

3 CMOS VLSI Design3 Sequencing  Combinational logic –output depends on current inputs  Sequential logic –output depends on current and previous inputs –Requires separating previous, current, future –Called state or tokens –Ex: FSM, pipeline

4 CMOS VLSI Design4 Sequencing Cont.  If tokens moved through pipeline at constant speed, no sequencing elements would be necessary  Ex: fiber-optic cable –Light pulses (tokens) are sent down cable –Next pulse sent before first reaches end of cable –No need for hardware to separate pulses –But dispersion sets min time between pulses  This is called wave pipelining in circuits  In most circuits, dispersion is high –Delay fast tokens so they don’t catch slow ones.

5 CMOS VLSI Design5 Sequencing Overhead  Use flip-flops to delay fast tokens so they move through exactly one stage each cycle.  Inevitably adds some delay to the slow tokens  Makes circuit slower than just the logic delay –Called sequencing overhead  Some people call this clocking overhead –But it applies to asynchronous circuits too –Inevitable side effect of maintaining sequence

6 CMOS VLSI Design6 Sequencing Elements  Latch: Level sensitive –a.k.a. transparent latch, D latch  Flip-flop: edge triggered –A.k.a. master-slave flip-flop, D flip-flop, D register  Timing Diagrams –Transparent –Opaque –Edge-trigger

7 CMOS VLSI Design7 Sequencing Elements  Latch: Level sensitive –a.k.a. transparent latch, D latch  Flip-flop: edge triggered –A.k.a. master-slave flip-flop, D flip-flop, D register  Timing Diagrams –Transparent –Opaque –Edge-trigger

8 CMOS VLSI Design8 Latch Design  Pass Transistor Latch  Pros +  Cons –

9 CMOS VLSI Design9 Latch Design  Pass Transistor Latch  Pros +Tiny +Low clock load  Cons –V t drop –nonrestoring –backdriving –output noise sensitivity –dynamic –diffusion input Used in 1970’s

10 CMOS VLSI Design10 Latch Design  Transmission gate + -

11 CMOS VLSI Design11 Latch Design  Transmission gate +No V t drop - Requires inverted clock

12 CMOS VLSI Design12 Latch Design  Inverting buffer + +Fixes either –

13 CMOS VLSI Design13 Latch Design  Inverting buffer +Restoring +No backdriving +Fixes either Output noise sensitivity Or diffusion input –Inverted output

14 CMOS VLSI Design14 Latch Design  Tristate feedback + –

15 CMOS VLSI Design15 Latch Design  Tristate feedback +Static –Backdriving risk  Static latches are now essential

16 CMOS VLSI Design16 Latch Design  Buffered input +

17 CMOS VLSI Design17 Latch Design  Buffered input +Fixes diffusion input +Noninverting

18 CMOS VLSI Design18 Latch Design  Buffered output +

19 CMOS VLSI Design19 Latch Design  Buffered output +No backdriving  Widely used in standard cells + Very robust (most important) -Rather large -Rather slow (1.5 – 2 FO4 delays) -High clock loading

20 CMOS VLSI Design20 Latch Design  Datapath latch + -

21 CMOS VLSI Design21 Latch Design  Datapath latch +Smaller, faster - unbuffered input

22 CMOS VLSI Design22 Flip-Flop Design  Flip-flop is built as pair of back-to-back latches

23 CMOS VLSI Design23 Enable  Enable: ignore clock when en = 0 –Mux: increase latch D-Q delay –Clock Gating: increase en setup time, skew

24 CMOS VLSI Design24 Reset  Force output low when reset asserted  Synchronous vs. asynchronous

25 CMOS VLSI Design25 Set / Reset  Set forces output high when enabled  Flip-flop with asynchronous set and reset

26 CMOS VLSI Design26 Sequencing Methods  Flip-flops  2-Phase Latches  Pulsed Latches

27 CMOS VLSI Design27 Review Timing Definitions

28 CMOS VLSI Design28 Timing Diagrams t pd Logic Prop. Delay t cd Logic Cont. Delay t pcq Latch/Flop Clk-Q Prop Delay t ccq Latch/Flop Clk-Q Cont. Delay t pdq Latch D-Q Prop Delay t pcq Latch D-Q Cont. Delay t setup Latch/Flop Setup Time t hold Latch/Flop Hold Time Contamination and Propagation Delays

29 CMOS VLSI Design29 Max-Delay: Flip-Flops 1. rising edge of clk trigger F1 2. data at Q1 after clk-to-Q delay t pcq 3. cont. logic delay to D2 4. setup time for F2 before rising edge of clk

30 CMOS VLSI Design30 Max-Delay: Flip-Flops t pd is the time allow for combinational logic design the CL block satisfying the constraint

31 CMOS VLSI Design31 Max Delay: 2-Phase Latches

32 CMOS VLSI Design32 Max Delay: 2-Phase Latches assume that t pdq1 = t pdq2 propagation delay D1 to Q1, D2 to Q2

33 CMOS VLSI Design33 Max Delay: Pulsed Latches t pdq : D to Q propa. delay t cdq : D to Q contamination delay t pcq : clk to Q propagation delay

34 CMOS VLSI Design34 Max Delay: Pulsed Latches If the pulse is wide enough, t pw > t setup, max-delay constraint is similar to the two-phase latches except only one latch is in the critical path t pd < T c - t pdq If pulse width is narrow than the setup time, data must set up before the pulse rises t pd < T c + t pw – t pcq – t setup

35 CMOS VLSI Design35 Min-Delay: Flip-Flops t cd minimum logic contamination delay If t hold > t cd, the data can incorrectly propagate through F1 and F2 two successive flip flops on one clock edge, resulting in system failure

36 CMOS VLSI Design36 Min-Delay: Flip-Flops 1. rising edge of clk trigger F1 2. after clk-to-Q cont. delay Q1 begins change 3. D2 begins to change after CL cont delay 4. D2 should not change for at least t hold w.r.t. the rising clk, if D2 changes it corrupts F2 so t cd minimum logic contamination delay of CL block

37 CMOS VLSI Design37 Min-Delay: 2-Phase Latches 1. Data pass through L1 from rising edge of  1 2. Data should not reach L2 until a hold time delay the previous falling edge of  2 i.e. L2 becomes safely opaque. We need t cd large enough to have correct operation, meet t hold requirement of L2

38 CMOS VLSI Design38 Min-Delay: 2-Phase Latches Hold time reduced by nonoverlap Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches! Contamination delay constraint applies to each phase of logic for latch- based systems, but to the entire cycle of logic for flip-flops.

39 CMOS VLSI Design39 Min-Delay: Pulsed Latches Hold time increased by pulse width

40 CMOS VLSI Design40 Min-Delay: Pulsed Latches Hold time increased by pulse width t ccq + t cd  t pw + t hold

41 CMOS VLSI Design41 Time Borrowing  In a flop-based system: –Data launches on one rising edge –Must setup before next rising edge –If it arrives late, system fails –If it arrives early, time is wasted –Flops have hard edges  In a latch-based system –Data can pass through latch while transparent –Long cycle of logic can borrow time into next –As long as each loop completes in one cycle

42 CMOS VLSI Design42 Time Borrowing Example

43 CMOS VLSI Design43 How Much Borrowing? 2-Phase Latches Pulsed Latches Data can depart the first latch on the rising edge of the clock and does not have to set up until the falling edge of the clock on the receiving latch

44 CMOS VLSI Design44 Clock Skew  We have assumed zero clock skew  Clocks really have uncertainty in arrival time –Decreases maximum propagation delay –Increases minimum contamination delay –Decreases time borrowing

45 CMOS VLSI Design45 Skew: Flip-Flops t ccq + t cd  t skew + t hold Launching flop receives its clock early, the receiving flop receives its clock late  clock skew effectively increases the hold time t pd : propagation delay of CL t cd : contamination delay of CL t pd

46 CMOS VLSI Design46 Skew: Latches 2-Phase Latches Latch-based design, clock skew does not degrade performance Data arrives at the latches while they are transparent even clocks are skewed. Latch based design systems are skew-tolerant.

47 CMOS VLSI Design47 Skew: Pulsed Latches Pulsed Latches If the pulse width is wide enough, the skew will not increase overhead If the pulse width is narrow, skew can degrade the performance

48 CMOS VLSI Design48 Two-Phase Clocking  If setup times are violated, reduce clock speed  If hold times are violated, chip fails at any speed  An easy way to guarantee hold times is to use 2- phase latches with big nonoverlap times  Call these clocks  1,  2 (ph1, ph2)

49 CMOS VLSI Design49 Safe Flip-Flop In industry, use a better timing analyzer –Add buffers to slow signals if hold time is at risk Power PC 603 datapath used this flip-flop

50 CMOS VLSI Design50 Differential Flip-flops Accepts true and complementary inputs Produce true and complementary outputs Works well for low-swing inputs such as register file bitlines and low-swing busses When  is low, precharge X, X’ When  is high, either X or X’ is pulled down, cross-coupled pMOS work as a keeper Cross-coupled NAND gates work as a SR latch capturing and holding the data.

51 CMOS VLSI Design51 Differential Flip-flops Replace the cross-coupled NAND gates by a faster latch

52 CMOS VLSI Design52 Summary  Flip-Flops: –Very easy to use, supported by all tools  2-Phase Transparent Latches: –Lots of skew tolerance and time borrowing  Pulsed Latches: –Fast, lowest sequencing overhead, susceptible to min- delay problem


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