Presentation on theme: "Introduction to CMOS VLSI Design Sequential Circuits"— Presentation transcript:
1 Introduction to CMOS VLSI Design Sequential Circuits
2 Outline Sequencing Sequencing Element Design Max and Min-Delay Clock SkewTime BorrowingTwo-Phase Clocking
3 Sequencing Combinational logic output depends on current inputs Sequential logicoutput depends on current and previous inputsRequires separating previous, current, futureCalled state or tokensEx: FSM, pipeline
4 Sequencing Cont.If tokens moved through pipeline at constant speed, no sequencing elements would be necessaryEx: fiber-optic cableLight pulses (tokens) are sent down cableNext pulse sent before first reaches end of cableNo need for hardware to separate pulsesBut dispersion sets min time between pulsesThis is called wave pipelining in circuitsIn most circuits, dispersion is highDelay fast tokens so they don’t catch slow ones.
5 Sequencing OverheadUse flip-flops to delay fast tokens so they move through exactly one stage each cycle.Inevitably adds some delay to the slow tokensMakes circuit slower than just the logic delayCalled sequencing overheadSome people call this clocking overheadBut it applies to asynchronous circuits tooInevitable side effect of maintaining sequence
6 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, D latchFlip-flop: edge triggeredA.k.a. master-slave flip-flop, D flip-flop, D registerTiming DiagramsTransparentOpaqueEdge-trigger
7 Sequencing Elements Latch: Level sensitive a.k.a. transparent latch, D latchFlip-flop: edge triggeredA.k.a. master-slave flip-flop, D flip-flop, D registerTiming DiagramsTransparentOpaqueEdge-trigger
32 Max Delay: 2-Phase Latches assume that tpdq1 = tpdq2propagation delay D1 to Q1, D2 to Q2
33 Max Delay: Pulsed Latches tpdq : D to Q propa. delaytcdq : D to Q contamination delaytpcq : clk to Q propagation delay
34 Max Delay: Pulsed Latches If the pulse is wide enough, tpw > tsetup , max-delay constraint is similar to the two-phase latches except only one latch is in the critical pathtpd < Tc - tpdqIf pulse width is narrow than the setup time, data must set up before the pulse risestpd < Tc + tpw – tpcq – tsetup
35 Min-Delay: Flip-Flops tcd minimum logic contamination delayIf thold > tcd, the data can incorrectly propagate through F1 and F2 two successive flip flops on one clock edge, resulting in system failure
36 Min-Delay: Flip-Flops tcd minimum logic contamination delay of CL block1. rising edge of clk trigger F12. after clk-to-Q cont. delayQ1 begins change3. D2 begins to change after CL cont delay4. D2 should not change for at least thold w.r.t. the rising clk, if D2 changes it corrupts F2so
37 Min-Delay: 2-Phase Latches 1. Data pass through L1 from rising edge of 12. Data should not reach L2 until a hold time delay the previous falling edge of 2 i.e. L2 becomes safely opaque.We need tcd large enough to have correct operation, meet thold requirement of L2
38 Min-Delay: 2-Phase Latches Hold time reduced by nonoverlapParadox: hold applies twice each cycle, vs. only once for flops.But a flop is made of two latches!Contamination delay constraint applies to each phase of logic for latch-based systems, but to the entire cycle of logic for flip-flops.
39 Min-Delay: Pulsed Latches Hold time increased by pulse width
40 Min-Delay: Pulsed Latches Hold time increased by pulse widthtccq + tcd tpw + thold
41 Time Borrowing In a flop-based system: Data launches on one rising edgeMust setup before next rising edgeIf it arrives late, system failsIf it arrives early, time is wastedFlops have hard edgesIn a latch-based systemData can pass through latch while transparentLong cycle of logic can borrow time into nextAs long as each loop completes in one cycle
43 How Much Borrowing? 2-Phase Latches Pulsed Latches Data can depart the first latch on the rising edge of the clock and does not have to set up until the falling edge of the clock on the receiving latch
44 Clock Skew We have assumed zero clock skew Clocks really have uncertainty in arrival timeDecreases maximum propagation delayIncreases minimum contamination delayDecreases time borrowing
45 Skew: Flip-Flops tpd : propagation delay of CL tpd tcd : contamination delay of CLtccq + tcd tskew + tholdLaunching flop receives its clock early, the receiving flop receives its clock late clock skew effectively increases the hold time
46 Skew: Latches 2-Phase Latches Latch-based design, clock skew does not degrade performanceData arrives at the latches while they are transparent even clocks are skewed.Latch based design systems are skew-tolerant.
47 Skew: Pulsed Latches Pulsed Latches If the pulse width is wide enough, the skew will not increase overheadIf the pulse width is narrow, skew can degrade the performance
48 Two-Phase Clocking If setup times are violated, reduce clock speed If hold times are violated, chip fails at any speedAn easy way to guarantee hold times is to use 2-phase latches with big nonoverlap timesCall these clocks f1, f2 (ph1, ph2)
49 Safe Flip-Flop In industry, use a better timing analyzer Add buffers to slow signals if hold time is at riskPower PC 603 datapath used this flip-flop
50 Differential Flip-flops Accepts true and complementaryinputsProduce true and complementaryoutputsWorks well for low-swing inputssuch as register file bitlines andlow-swing bussesWhen is low, precharge X, X’When is high, either X or X’ is pulled down, cross-coupled pMOS work as a keeperCross-coupled NAND gates work as a SR latch capturing and holding the data .
51 Differential Flip-flops Replace the cross-coupled NAND gates by a faster latch
52 Summary Flip-Flops: Very easy to use, supported by all tools 2-Phase Transparent Latches:Lots of skew tolerance and time borrowingPulsed Latches:Fast, lowest sequencing overhead, susceptible to min-delay problem