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1: Circuits & LayoutSlide 1EE 447 VLSI Design VLSI Design Circuits & Layout.

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Presentation on theme: "1: Circuits & LayoutSlide 1EE 447 VLSI Design VLSI Design Circuits & Layout."— Presentation transcript:

1 1: Circuits & LayoutSlide 1EE 447 VLSI Design VLSI Design Circuits & Layout

2 1: Circuits & LayoutSlide 2EE 447 VLSI Design Outline  CMOS Gate Design  Pass Transistors  CMOS Latches & Flip-Flops  Standard Cell Layouts  Stick Diagrams

3 1: Circuits & LayoutSlide 3EE 447 VLSI Design CMOS Gate Design  A 4-input CMOS NOR gate

4 1: Circuits & LayoutSlide 4EE 447 VLSI Design Complementary CMOS  Complementary CMOS logic gates –nMOS pull-down network –pMOS pull-up network –a.k.a. static CMOS X (crowbar)0Pull-down ON 1Z (float)Pull-down OFF Pull-up ONPull-up OFF

5 1: Circuits & LayoutSlide 5EE 447 VLSI Design Series and Parallel  nMOS: 1 = ON  pMOS: 0 = ON  Series: both must be ON  Parallel: either can be ON

6 1: Circuits & LayoutSlide 6EE 447 VLSI Design Conduction Complement  Complementary CMOS gates always produce 0 or 1  Ex: NAND gate –Series nMOS: Y=0 when both inputs are 1 –Thus Y=1 when either input is 0 –Requires parallel pMOS  Rule of Conduction Complements –Pull-up network is complement of pull-down –Parallel -> series, series -> parallel

7 1: Circuits & LayoutSlide 7EE 447 VLSI Design Compound Gates  Compound gates can do any inverting function  Ex:

8 1: Circuits & LayoutSlide 8EE 447 VLSI Design Example: O3AI 

9 1: Circuits & LayoutSlide 9EE 447 VLSI Design Example: O3AI 

10 1: Circuits & LayoutSlide 10EE 447 VLSI Design Pass Transistors  Transistors can be used as switches

11 1: Circuits & LayoutSlide 11EE 447 VLSI Design Pass Transistors  Transistors can be used as switches

12 1: Circuits & LayoutSlide 12EE 447 VLSI Design Signal Strength  Strength of signal –How close it approximates ideal voltage source  V DD and GND rails are strongest 1 and 0  nMOS pass strong 0 –But degraded or weak 1  pMOS pass strong 1 –But degraded or weak 0  Thus NMOS are best for pull-down network  Thus PMOS are best for pull-up network

13 1: Circuits & LayoutSlide 13EE 447 VLSI Design Transmission Gates  Pass transistors produce degraded outputs  Transmission gates pass both 0 and 1 well

14 1: Circuits & LayoutSlide 14EE 447 VLSI Design Transmission Gates  Pass transistors produce degraded outputs  Transmission gates pass both 0 and 1 well

15 1: Circuits & LayoutSlide 15EE 447 VLSI Design Tristates  Tristate buffer produces Z when not enabled Z10 Z00 YAEN

16 1: Circuits & LayoutSlide 16EE 447 VLSI Design Nonrestoring Tristate  Transmission gate acts as tristate buffer –Only two transistors –But nonrestoring Noise on A is passed on to Y (after several stages, the noise may degrade the signal beyond recognition)

17 1: Circuits & LayoutSlide 17EE 447 VLSI Design Tristate Inverter  Tristate inverter produces restored output –Violates conduction complement rule –Because we want a Z output

18 1: Circuits & LayoutSlide 18EE 447 VLSI Design Tristate Inverter  Tristate inverter produces restored output –Violates conduction complement rule –Because we want a Z output

19 1: Circuits & LayoutSlide 19EE 447 VLSI Design Multiplexers  2:1 multiplexer chooses between two inputs X11 X01 1X0 0X0 YD0D1S

20 1: Circuits & LayoutSlide 20EE 447 VLSI Design Multiplexers  2:1 multiplexer chooses between two inputs 1X11 0X01 11X0 00X0 YD0D1S

21 1: Circuits & LayoutSlide 21EE 447 VLSI Design Gate-Level Mux Design   How many transistors are needed?

22 1: Circuits & LayoutSlide 22EE 447 VLSI Design Gate-Level Mux Design   How many transistors are needed? 20

23 1: Circuits & LayoutSlide 23EE 447 VLSI Design Transmission Gate Mux  Nonrestoring mux uses two transmission gates

24 1: Circuits & LayoutSlide 24EE 447 VLSI Design Transmission Gate Mux  Nonrestoring mux uses two transmission gates –Only 4 transistors

25 1: Circuits & LayoutSlide 25EE 447 VLSI Design Inverting Mux  Inverting multiplexer –Use compound AOI22 –Or pair of tristate inverters –Essentially the same thing  Noninverting multiplexer adds an inverter

26 1: Circuits & LayoutSlide 26EE 447 VLSI Design 4:1 Multiplexer  4:1 mux chooses one of 4 inputs using two selects

27 1: Circuits & LayoutSlide 27EE 447 VLSI Design 4:1 Multiplexer  4:1 mux chooses one of 4 inputs using two selects –Two levels of 2:1 muxes –Or four tristates

28 1: Circuits & LayoutSlide 28EE 447 VLSI Design D Latch  When CLK = 1, latch is transparent –Q follows D (a buffer with a Delay)  When CLK = 0, the latch is opaque –Q holds its last value independent of D  a.k.a. transparent latch or level-sensitive latch

29 1: Circuits & LayoutSlide 29EE 447 VLSI Design D Latch Design  Multiplexer chooses D or old Q

30 1: Circuits & LayoutSlide 30EE 447 VLSI Design D Latch Operation

31 1: Circuits & LayoutSlide 31EE 447 VLSI Design D Flip-flop  When CLK rises, D is copied to Q  At all other times, Q holds its value  a.k.a. positive edge-triggered flip-flop, master-slave flip-flop

32 1: Circuits & LayoutSlide 32EE 447 VLSI Design D Flip-flop Design  Built from master and slave D latches A “negative level-sensitive” latchA “positive level-sensitive” latch

33 1: Circuits & LayoutSlide 33EE 447 VLSI Design D Flip-flop Operation Inverted version of D Inverts NOT(QM) and holds it. Hold the last value of NOT D

34 1: Circuits & LayoutSlide 34EE 447 VLSI Design Race Condition  Back-to-back flops can malfunction from clock skew –Second flip-flop fires Early –Sees first flip-flop change and captures its result –Called hold-time failure or race condition

35 1: Circuits & LayoutSlide 35EE 447 VLSI Design Nonoverlapping Clocks  Nonoverlapping clocks can prevent races –As long as nonoverlap exceeds clock skew  We will use them in this class for safe design –Industry manages skew more carefully instead

36 1: Circuits & LayoutSlide 36EE 447 VLSI Design Gate Layout  Layout can be very time consuming –Design gates to fit together nicely –Build a library of standard cells  Standard cell design methodology –V DD and GND should abut (standard height) –Adjacent gates should satisfy design rules –nMOS at bottom and pMOS at top –All gates include well and substrate contacts

37 1: Circuits & LayoutSlide 37EE 447 VLSI Design Example: Inverter

38 1: Circuits & LayoutSlide 38EE 447 VLSI Design Inverter, contd..

39 1: Circuits & LayoutSlide 39EE 447 VLSI Design Example: NAND3  Horizontal N-diffusion and p-diffusion strips  Vertical polysilicon gates  Metal1 V DD rail at top  Metal1 GND rail at bottom  32 by 40

40 1: Circuits & LayoutSlide 40EE 447 VLSI Design NAND3, contd.

41 1: Circuits & LayoutSlide 41EE 447 VLSI Design Stick Diagrams  Stick diagrams help plan layout quickly –Need not be to scale –Draw with color pencils or dry-erase markers

42 1: Circuits & LayoutSlide 42EE 447 VLSI Design Stick Diagrams  Stick diagrams help plan layout quickly –Need not be to scale –Draw with color pencils or dry-erase markers Vin Vout VDD GND

43 1: Circuits & LayoutSlide 43EE 447 VLSI Design Wiring Tracks  A wiring track is the space required for a wire –4 width, 4 spacing from neighbor = 8 pitch  Transistors also consume one wiring track

44 1: Circuits & LayoutSlide 44EE 447 VLSI Design Well spacing  Wells must surround transistors by 6 –Implies 12 between opposite transistor flavors –Leaves room for one wire track

45 1: Circuits & LayoutSlide 45EE 447 VLSI Design Area Estimation  Estimate area by counting wiring tracks –Multiply by 8 to express in

46 1: Circuits & LayoutSlide 46EE 447 VLSI Design Example: O3AI  Sketch a stick diagram for O3AI and estimate area –

47 1: Circuits & LayoutSlide 47EE 447 VLSI Design Example: O3AI  Sketch a stick diagram for O3AI and estimate area –

48 1: Circuits & LayoutSlide 48EE 447 VLSI Design Example: O3AI  Sketch a stick diagram for O3AI and estimate area –


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