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CPS3340 COMPUTER ARCHITECTURE Fall Semester, 2013 09/23/2013 Lecture 7: Computer Clock & Memory Elements Instructor: Ashraf Yaseen DEPARTMENT OF MATH &

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Presentation on theme: "CPS3340 COMPUTER ARCHITECTURE Fall Semester, 2013 09/23/2013 Lecture 7: Computer Clock & Memory Elements Instructor: Ashraf Yaseen DEPARTMENT OF MATH &"— Presentation transcript:

1 CPS3340 COMPUTER ARCHITECTURE Fall Semester, /23/2013 Lecture 7: Computer Clock & Memory Elements Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER SCIENCE CENTRAL STATE UNIVERSITY, WILBERFORCE, OH 1

2 Review  Last Class  ALU  This Class  Computer Clock  Memory Elements  Next Class  Memory Unit  Error Detection and Correction 2

3 Computer Clocks  CPU clock  Generated by an oscillator crystal  Produce a fixed waveform  Clock rate of a CPU is determined by the frequency of the oscillator crystal  Clocks are needed in sequential logic to decide when an element that contains state should be updated. 3

4 Clock Cycle  Clock cycle time (clock period)  Two portions Clock is high Clock is low  Edge-triggered clocking  All state changes occur on a clock edge 4

5 State Element and Valid State  State Element  A memory element  Signals written into state elements must be valid when the active clock edge occurs  Valid means stable (not changing) Will not change again until the inputs change  Synchronous System  A memory system that employs clocks and where data signals are read only when the clock indicates that the signal values are stable 5

6  Inputs to a combinational logic block from a state element, and the outputs are written into a state element  Clock edge determines when the state elements are updated 6

7 Read and Write in one cycle  Edge-triggered methodology allows a state element to be read and written in the same clock cycle  Read the value of a state element  Send it through some combinational logic Value does not change during the clock cycle  Write it back to the same state element  All in one cycle 7

8 Memory Elements  Memory Elements  Store States  Output depends on The inputs, and The value stored in the memory element  Elements  Flip-Flops, Latches  Registers & Register Files  SRAMS, DRAMS 8

9 Set-Reset Latch (S-R Latch)  A pair of cross-coupled NOR gates  Unclocked Do not have a clock input  Can store an internal value Q represent the current state 9

10 S-R Latch (Cont.)  S=0 and R=0  NOR gates are equivalent to inverters  Previous States are stored  S=1 and R=0  Q=1 and ~Q=0  S=0 and R=1  Q=0 and ~Q=1  S=1 and R=1  Oscillated, metastable 10

11 Flip-flops & Latches  Flip-flop:  A memory element for which the output is equal to the value of the stored state inside the element and for which the internal state is changed only on a clock edge.  Latch:  state is changed whenever the appropriate inputs change and the clock is asserted D-Latch (D-Flip-flop) Clock input C Data input D Flip-flops and latches are the simplest memory elements 11

12  When the clock input C is a sserted, the latch is said to be open,  the value of the output (Q) becomes the value of the input D.  When the clock input C is deasserted, the latch is said to be closed,  the value of the out put (Q) is whatever value was stored the last time the latch was open 12

13 Operation of a D-Latch  Operation of a D latch, assuming the output is initially deasserted. When the clock, C, is asserted, the latch is open and the Q output immediately assumes the value of the D input 13

14 Difference btw. Latch and Flip-flop  Latch  Asynchronous Output changes soon after input changes when the clock is asserted  Flip-flop  Synchronous Output changes at the clock edge 14

15 More on D-Latch  Q changes as D changes when clock is up  Not really edge-triggered 15

16 D Flip Flop  D Flip Flop with a Falling-Edge Trigger The first latch, called the master, is open and follows the input D when the clock input, C, is asserted. When the clock input, C, falls, the first latch is closed, but the second latch, called the slave, is open and gets its input from the output of the master latch. 16

17 Operation of D Flip Flop  D Flip Flop with a Falling Edge Trigger When the clock input (C) changes from asserted to deasserted, the Q output stores the value of the D input. 17

18 Setup Time and Hold Time  The input must be stable for a period of time before and after the clock edge  Setup Time The minimum time the signal must be stable before clock edge  Hold Time The minimum time the signal must be stable after clock edge Usually very small 18

19 Register Files  A register file consists of a set of registers that can be read and written by supplying a register number  Built from an array of D Flip-Flops  A decoder is used to select a register in the register file A register file with two read ports and one write port has five inputs and two outputs 19

20 Reading Registers  Multiplexor  Select data from the specific register 20

21 Writing to a register  Write Signal  Specify a write operation to the register  Decoder  Specify which register to write  Register Data  Data to write to the register 21

22 Register Files  Register Files  Can be used to build small memory  Too costly to build large amount of memory  Large Scale Memory  Static random access memories (SRAM)  Dynamic random access memories (DRAM) 22

23 Summary  Computer Clock  Rising Edge and Falling Edge  Edge Triggered Clocking  Memory Elements  S-R Latch  Flip-Flop  Register File 23

24 What I want you to do  Review Appendix C 24


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