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1 COMP541 Flip-Flop Timing Montek Singh Oct 6, 2014

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Topics Timing analysis flip-flops flip-flops sequential systems sequential systems clock skew clock skew 2

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Lab 7: VGA Display Anyone having trouble with Lab 7? Be careful about the “Sync Polarity” A “1” means a downward going pulse A “1” means a downward going pulse sync signal is normally high, but goes low during the pulse A “0” means an upward going pulse A “0” means an upward going pulse Use my self-checking text bench! simulates my VGA driver … simulates my VGA driver … … and compares your outputs with mine … and compares your outputs with mine flags any mismatches flags any mismatches 3

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Timing of sequential circuits 4

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Input Timing Constraints Setup time: t setup = time before the clock edge that data must be stable (i.e. not changing) Hold time: t hold = time after the clock edge that data must be stable Aperture time: t a = time around clock edge that data must be stable (t a = t setup + t hold )

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Output Timing Constraints Propagation delay: t pcq = max time after clock edge by which output Q is guaranteed to have stabilized (i.e., not changing anymore) Contamination delay: t ccq = min time after clock edge during which Q will not have started changing yet

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Dynamic Discipline The input to a synchronous sequential circuit must be stable during the aperture (setup and hold) time around the clock edge Specifically, the input must be stable at least t setup before the clock edge at least t setup before the clock edge at least until t hold after the clock edge at least until t hold after the clock edge

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Implications on Design Constrains operation Given a clock period, constrains circuit delays Given a clock period, constrains circuit delays Given a circuit, constraints clock period Given a circuit, constraints clock period The delay between registers (which impacts clock period) has a minimum and maximum delay, dependent on the delays of the circuit elements Delays of both comb. logic and flip-flops must be taken into account Delays of both comb. logic and flip-flops must be taken into account

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Setup Time Constraint Setup time input to R2 must be stable at least t setup before the clock edge input to R2 must be stable at least t setup before the clock edge constrains max delay from R1 through combinational logic constrains max delay from R1 through combinational logic What’s min clock period? What’s T c? T c ≥ t pcq + t pd + t setup t pd ≤ T c – (t pcq + t setup ) So, clock period constrained by: Delay in CL Delay in previous reg (R1) Setup requirement in next reg (R2)

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Hold Time Constraint Hold time input to R2 must be stable for at least t hold after clock edge input to R2 must be stable for at least t hold after clock edge constrains the minimum delay from register R1 through the combinational logic constrains the minimum delay from register R1 through the combinational logic often try to design circuits with 0 hold time requirement often try to design circuits with 0 hold time requirement t hold < t ccq + t cd t cd > t hold - t ccq

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Timing Analysis Timing Characteristics t ccq = 30 ps (FF contamination) t pcq = 50 ps (FF propagation) t setup = 60 ps t hold = 70 ps t pd = 35 ps t cd = 25 ps t pd = t cd = Setup time constraint: T c ≥ f c = Hold time constraint: t ccq + t cd > t hold ? t pd = 3 x 35 ps = 105 ps t cd = 25 ps Setup time constraint: T c ≥ ( ) ps = 215 ps f c = 1/T c = 4.65 GHz ( ) ps > 70 ps ? No!

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Fixing Hold Time Violation Timing Characteristics t ccq = 30 ps t pcq = 50 ps t setup = 60 ps t hold = 70 ps t pd = 35 ps t cd = 25 ps t pd = 3 x 35 ps = 105 ps t cd = 2 x 25 ps = 50 ps Setup time constraint: T c ≥ ( ) ps = 215 ps f c = 1/T c = 4.65 GHz Hold time constraint: t ccq + t pd > t hold ? ( ) ps > 70 ps ? Yes! Add buffers to the short paths:

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Hold Time Often flip-flops are designed for a hold time of zero To avoid these tricky problems To avoid these tricky problems

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Clock Skew Clock doesn’t arrive at all registers at the same time Skew is the difference between the arrival times of the clock edge at two different (typically neighboring) flip-flops Skew is the difference between the arrival times of the clock edge at two different (typically neighboring) flip-flops Examine the worst case: guarantee that discipline is not violated for any register pair guarantee that discipline is not violated for any register pair many registers in a system! many registers in a system!

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Setup Time Constraint with Clock Skew Worst case: CLK2 is earlier than CLK1 T c ≥ t pcq + t pd + t setup + t skew t pd ≤ T c – (t pcq + t setup + t skew )

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Similar Issue w/ Hold Time We won’t go over example Have a look in book Have a look in book 16

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Next Time Read Section Then we’ll move on to memories Section 5.5 Section

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