Presentation is loading. Please wait.

Presentation is loading. Please wait.

Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout Manoel E. de Lima – CIn – UFPE David Harris Harvey Mudd College Spring 2004.

Similar presentations


Presentation on theme: "Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout Manoel E. de Lima – CIn – UFPE David Harris Harvey Mudd College Spring 2004."— Presentation transcript:

1 Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout Manoel E. de Lima – CIn – UFPE David Harris Harvey Mudd College Spring 2004

2 CMOS VLSI Design1: Circuits & LayoutSlide 2 Outline  CMOS Gate Design  Pass Transistors  CMOS Latches & Flip-Flops  Standard Cell Layouts  Stick Diagrams

3 CMOS VLSI Design1: Circuits & LayoutSlide 3 CMOS Gate Design  Activity: –Sketch a 4-input CMOS NAND gate

4 CMOS VLSI Design1: Circuits & LayoutSlide 4 CMOS Gate Design  Activity: –Sketch a 4-input CMOS NOR gate

5 CMOS VLSI Design1: Circuits & LayoutSlide 5 Complementary CMOS  Complementary CMOS logic gates –nMOS pull-down network –pMOS pull-up network Pull-up OFFPull-up ON Pull-down OFFZ (float)1 Pull-down ON0X (crowbar)

6 CMOS VLSI Design1: Circuits & LayoutSlide 6 Series and Parallel  nMOS: 1 = ON  pMOS: 0 = ON  Series: both must be ON  Parallel: either can be ON

7 CMOS VLSI Design1: Circuits & LayoutSlide 7 Conduction Complement  Complementary CMOS gates always produce 0 or 1  Ex: NAND gate –Series nMOS: Y=0 when both inputs are 1 –Thus Y=1 when either input is 0 –Requires parallel pMOS  Rule of Conduction Complements –Pull-up network is complement of pull-down –Parallel -> series, series -> parallel

8 CMOS VLSI Design1: Circuits & LayoutSlide 8 Compound Gates  Compound gates can do any inverting function  Ex: A.B+C.D AB CD nMOS pMOS nMOS+pMOS

9 CMOS VLSI Design  Y = (A+B+C).D Vcc 1: Circuits & LayoutSlide 9 Example: O3AI

10 CMOS VLSI Design1: Circuits & LayoutSlide 10 Signal Strength  Strength of signal –How close it approximates ideal voltage source  V DD and GND rails are strongest 1 and 0  nMOS pass strong 0 –But degraded or weak 1  pMOS pass strong 1 –But degraded or weak 0  Thus nMOS are best for pull-down network

11 CMOS VLSI Design1: Circuits & LayoutSlide 11 Pass Transistors  Transistors can be used as switches

12 CMOS VLSI Design1: Circuits & LayoutSlide 12 Pass Transistors  Transistors can be used as switches

13 CMOS VLSI Design1: Circuits & LayoutSlide 13 Transmission Gates  Pass transistors produce degraded outputs  Transmission gates pass both 0 and 1 well

14 CMOS VLSI Design1: Circuits & LayoutSlide 14 Transmission Gates  Pass transistors produce degraded outputs  Transmission gates pass both 0 and 1 well

15 CMOS VLSI Design1: Circuits & LayoutSlide 15 Tristates  Tristate buffer produces Z when not enabled ENAY

16 CMOS VLSI Design1: Circuits & LayoutSlide 16 Tristates  Tristate buffer produces Z when not enabled ENAY 00Z 01Z

17 CMOS VLSI Design1: Circuits & LayoutSlide 17 Nonrestoring Tristate  Transmission gate acts as tristate buffer –Only two transistors\ Noise on A is passed on to Y

18 CMOS VLSI Design1: Circuits & LayoutSlide 18 Tristate Inverter  Tristate inverter produces restored output –Violates conduction complement rule –Because we want a Z output

19 CMOS VLSI Design1: Circuits & LayoutSlide 19 Tristate Inverter  Tristate inverter produces restored output –Violates conduction complement rule –Because we want a Z output

20 CMOS VLSI Design1: Circuits & LayoutSlide 20 Multiplexers  2:1 multiplexer chooses between two inputs SD1D0Y 0X0 0X1 10X 11X

21 CMOS VLSI Design1: Circuits & LayoutSlide 21 Multiplexers  2:1 multiplexer chooses between two inputs SD1D0Y 0X00 0X11 10X0 11X1

22 CMOS VLSI Design1: Circuits & LayoutSlide 22 Gate-Level Mux Design   How many transistors are needed?

23 CMOS VLSI Design1: Circuits & LayoutSlide 23 Gate-Level Mux Design   How many transistors are needed? 20

24 CMOS VLSI Design1: Circuits & LayoutSlide 24 Inverting Mux  Inverting multiplexer –Pair of tristate inverters –Essentially the same thing  Noninverting multiplexer adds an inverter

25 CMOS VLSI Design1: Circuits & LayoutSlide 25 Transmission Gate Mux  Two transmission gates –Only 4 transistors

26 CMOS VLSI Design1: Circuits & LayoutSlide 26 4:1 Multiplexer  4:1 mux chooses one of 4 inputs using two selects

27 CMOS VLSI Design1: Circuits & LayoutSlide 27 4:1 Multiplexer  4:1 mux chooses one of 4 inputs using two selects –Two levels of 2:1 muxes –Or four tristates

28 CMOS VLSI Design1: Circuits & LayoutSlide 28 D Latch  When CLK = 1, latch is transparent –D flows through to Q like a buffer  When CLK = 0, the latch is opaque –Q holds its old value independent of D  Transparent latch or level-sensitive latch

29 CMOS VLSI Design1: Circuits & LayoutSlide 29 D Latch Design  Multiplexer chooses D or old Q

30 CMOS VLSI Design1: Circuits & LayoutSlide 30 D Latch Operation

31 CMOS VLSI Design1: Circuits & LayoutSlide 31 D Flip-flop  When CLK rises, D is copied to Q  At all other times, Q holds its value  Positive edge-triggered flip-flop, master-slave flip- flop

32 CMOS VLSI Design1: Circuits & LayoutSlide 32 D Flip-flop Design  Built from master and slave D latches MasterSlave

33 CMOS VLSI Design1: Circuits & LayoutSlide 33 D Flip-flop Operation Master on Slave off Master of Slave on

34 CMOS VLSI Design1: Circuits & LayoutSlide 34 Race Condition  Back-to-back flops can malfunction from clock skew –Second flip-flop fires late –Sees first flip-flop change and captures its result –Called hold-time failure or race condition

35 CMOS VLSI Design1: Circuits & LayoutSlide 35 Nonoverlapping Clocks  Nonoverlapping clocks can prevent races –As long as nonoverlap exceeds clock skew  We will use them in this class for safe design –Industry manages skew more carefully instead


Download ppt "Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout Manoel E. de Lima – CIn – UFPE David Harris Harvey Mudd College Spring 2004."

Similar presentations


Ads by Google