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CPE 626 CPU Resources: Adders & Multipliers Aleksandar Milenkovic Web:http://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenka.

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Presentation on theme: "CPE 626 CPU Resources: Adders & Multipliers Aleksandar Milenkovic Web:http://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenka."— Presentation transcript:

1 CPE 626 CPU Resources: Adders & Multipliers Aleksandar Milenkovic Web:http://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenka

2 2 Outline  Full Adder  Ripple Carry Adder  Carry-Look-Ahead Adder  Manchester Adders  Carry Select Adder  Carry Skip Adder  Conditional Sum Adder  Hybrid Designs

3 3 Full Adder  Inputs  data inputs A, B  carry in C in  Outputs  sum S  carry out C out

4 4 Full Adder

5 5

6 6 Transmission-Gate Adder (1)  A = 1 => -A = 0 => TG is open => out = -B  A = 0 => -A = 1 => TG is closed => out = B  A = 1 => -A = 0 => TG is closed => out = B  A = 0 => -A = 1 => TG is open => out = -B TG XOR TG XNOR

7 7 Transmission-Gate Adder (2)

8 8 Ripple Carry Adder - RCA (1)  Method 1  G[i] = A[i]*B[i]  P[i] = A[i]  B[i]  C[i] = G[i] + P[i]*C[i-1]  S[i] = P[i]  C[i-1]  Method 2  G[i] = A[i]*B[i]  P[i] = A[i] + B[i]  C[i] = G[i] + P[i]*C[i-1]  S[i] = A[i]  B[i]  C[i-1]

9 9 Ripple Carry Adder - RCA (2)  Replace AND-OR pair with fast 2-inputs NAND gates RCA delay is proportional to n and is limited by the propagation of the carry signal through all of the stages

10 10 Ripple Carry Adder - RCA (3) Used in odd stages! Used in even stages!

11 11 Ripple Carry Adder - RCA (4)  Carry equations  C[i+1] = A[i]*B[i] + P[i]*C[i] or C[i+1] = (A[i] + B[i])*(P[i]’ + C[i]) P[i]’ = NOT(P[i])  Even stages  C1[i+1]’ = P[i]*C3[i]*C4[i]  C2[i+1] = A[i] + B[i]  C[i+1] = C1[i]*C2[i]  Odd stages  C3[i+1]’ = P[i]*C1[i]*C2[i]  C4[i+1]’ = A[i]*B[i]  C[i+1] = C3[i]’ + C4[i]’  Inputs to stage zero: C3[0] = C4[0] = ‘0’

12 12 Carry-Look-Ahead Adder – CLA (1)  Idea: speed up carry computation – C i+1 = G i + P i* C i  Propagate: P i = A i + B i  if P i = 1, then carry from (i-1)th stage is propagated  Generate: G i = A i *B i  if G i = 1 there is carry out

13 13 Carry-Look-Ahead Adder – CLA (2)

14 14 Carry-Look-Ahead Adder – CLA (3) Domino implementation (Dynamic Carry Gates)

15 15 Carry-Look-Ahead Adder – CLA (4)

16 16 Carry-Look-Ahead Adder – CLA (5)

17 17 Brent-Kung CLA  a) lookahead terms  b) CLG cell  c) cells can be rearranged into tree  d) simplified representations for part a)  e) simplified representation for part c)  f) lookahead logic for 8-bit adder  g) Brent-Kung adder Reduces delay, increases the regularity, reduces the number of unnecessary switching events (power)

18 18 Manchester Adder Circuits (1)

19 19 Manchester Adder Circuits (2) Dynamic Stage Static Stage MUX stage

20 20 4-bit Manchester Adder

21 21 Carry Bypass

22 22 Carry Select Adder (1) Compute 2 versions of the addition with different carry-ins, one assuming that the carry-in is 0 and another assuming that it is 1

23 23 Carry Select Adder (2)

24 24 Carry Skip Adder: Motivation Computing P 3-0 is much simpler than computing G 0-3 Let’s compute only P 3-0 !

25 25 Carry Skip Adder Carries begin rippling simultaneously through each block; If any block generates a carry, then the carry out will be true, even the carry-in may not be not true yet. If at the start of each add operation the carry-in to each block is 0, then correct carry-outs will be generated – carry-out can be thought of as if it is the G signal Practical only if the carry-in signals can be easily cleared at the start of each operation – e.g. precharging CMOS

26 26 Carry Skip Adder: Analysis  Assume  it takes 1 time unit for signal to propagate through two logic level  n bits wide adder  blocks of size k  It will take k units for a carry to ripple through a block of size k  Critical path  k units for the first block  n/k – 2 units to skip the blocks  k units to ripple through the last block  Increase the efficiency by varying the blocks size  20 bits (4, 4, 4, 4, 4,): Delay = = 11  20 bits (2, 5, 6, 5, 2): Delay = 9

27 27 Conditional Sum Adder (1)

28 28 Conditional Sum Adder (2)

29 29 Conditional Sum Adder (3) A B Si Ci Si Ci Si Ci Si Ci Si Ci 0 01 Si Ci S0S S1S

30 30 Hybrid Designs: An Example  Combine CLA (Carry Look-Ahead) with RCA


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